公开(公告)号：US07433233B2

公开(公告)日：2008-10-07

申请号：US11764793

申请日：2007-06-18

申请人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

发明人： En-Hsing Chen ,  Andrew J. Walker ,  Roy E. Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca G. Fasoli

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3418 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1159

摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

摘要翻译： 示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。 为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。 此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。 在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

公开(公告)号：US20080239790A1

公开(公告)日：2008-10-02

申请号：US11692144

申请日：2007-03-27

申请人： S. Brad Herner ,  Roy E. Scheuerlein

发明人： S. Brad Herner ,  Roy E. Scheuerlein

IPC分类号： G11C11/36

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L27/2481 ,  H01L27/285 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/149 ,  H01L51/0048 ,  H01L51/0595 ,  Y10S977/742

摘要： A method to form a rewriteable nonvolatile memory cell is disclosed, the cell comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels.

摘要翻译： 公开了一种形成可重写非易失性存储单元的方法，所述单元包括与碳纳米管织物串联的转向元件。 转向元件优选为二极管，但也可以是晶体管。 当经受适当的电脉冲时，碳纳米管织物可逆地改变电阻率。 可以感测碳纳米管织物的不同电阻率状态，并且可以对应于存储器单元的不同数据状态。 这种存储器单元的第一存储器级别可以单片地形成在衬底上方，第一存储器级单元形成在第一存储器之上，等等，形成堆叠存储器级别的高密度单片三维存储器阵列。

公开(公告)号：US20080192524A1

公开(公告)日：2008-08-14

申请号：US12102801

申请日：2008-04-14

申请人： Luca G. Fasoli ,  Roy E. Scheuerlein

发明人： Luca G. Fasoli ,  Roy E. Scheuerlein

IPC分类号： G11C5/02 ,  G11C8/00 ,  H01S4/00

CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/063 ,  G11C7/18 ,  G11C29/808 ,  H01L27/101 ,  H01L27/105 ,  Y10T29/49002

摘要： An integrated circuit having a three-dimensional memory array provides for a given number of memory planes, but may be fabricated instead to include a lesser number of memory planes by omitting the masks and processing steps associated with the omitted memory planes, without changing any of the other fabrication masks for the other memory planes or for the remainder of the device, and without requiring routing or other configuration changes to the read or read/write path for the array. Control circuitry for selectively enabling certain layer selector circuits is configurable, and the layer selector circuits are suitably arranged, to couple a respective array line on an implemented memory layer to each respective I/O bus line irrespective of the number of implemented memory planes.

摘要翻译： 具有三维存储器阵列的集成电路提供给定数量的存储器平面，但是可以通过省略与所省略的存储器平面相关联的掩模和处理步骤来替代地制造更少数量的存储器层，而不改变任何 用于其他存储器平面或其余器件的其他制造掩模，并且不需要对阵列的读取或读取/写入路径进行路由或其他配置更改。 用于选择性地启用某些层选择器电路的控制电路是可配置的，并且层选择器电路被适当地布置，以将实现的存储器层上的相应阵列线耦合到每个相应的I / O总线，而与所实现的存储器平面的数量无关。

公开(公告)号：US20080159052A1

公开(公告)日：2008-07-03

申请号：US11618843

申请日：2006-12-31

申请人： Tianhong Yan ,  Luca G. Fasoli ,  Roy E. Scheuerlein

发明人： Tianhong Yan ,  Luca G. Fasoli ,  Roy E. Scheuerlein

IPC分类号： G11C8/10

CPC分类号： G11C8/08

摘要： A reversible polarity decoder circuit is disclosed which is particularly suitable for implementing a multi-headed decoder structure, such as might be used for decoding word lines, and particularly in a 3D memory array. The decoder circuit provides an overdrive voltage bias to the gates of half-selected word line driver circuits to solidly maintain the half-selected word lines at an inactive level. If the memory array is biased at or near the breakdown voltage, this overdrive voltage may be greater than the breakdown voltage of the decoder transistors. However, in the embodiments described, the decoder circuit accomplishes this without impressing a voltage greater than the breakdown voltage across any of the decoder transistors, for either polarity of operation of the decoder circuit.

摘要翻译： 公开了一种可逆极性解码器电路，其特别适用于实现多头解码器结构，例如可用于解码字线，特别是在3D存储器阵列中。 解码器电路向半选择的字线驱动电路的栅极提供过驱动电压偏置，以将半选择的字线牢固地保持在非活动电平。 如果存储器阵列被偏置在或接近击穿电压，则该过驱动电压可能大于解码晶体管的击穿电压。 然而，在所描述的实施例中，解码器电路实现这一点，而不会对解码器电路的任一极性进行施加大于任何解码晶体管的击穿电压的电压。

公开(公告)号：US07359279B2

公开(公告)日：2008-04-15

申请号：US11095415

申请日：2005-03-31

申请人： Luca G. Fasoli ,  Roy E. Scheuerlein

发明人： Luca G. Fasoli ,  Roy E. Scheuerlein

IPC分类号： G11C8/00

CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/063 ,  G11C7/18 ,  G11C29/808 ,  H01L27/101 ,  H01L27/105 ,  Y10T29/49002

摘要： An integrated circuit having a three-dimensional memory array provides for a given number of memory planes, but may be fabricated instead to include a lesser number of memory planes by omitting the masks and processing steps associated with the omitted memory planes, without changing any of the other fabrication masks for the other memory planes or for the remainder of the device, and without requiring routing or other configuration changes to the read or read/write path for the array. Control circuitry for selectively enabling certain layer selector circuits is configurable, and the layer selector circuits are suitably arranged, to couple a respective array line on an implemented memory layer to each respective I/O bus line irrespective of the number of implemented memory planes.

摘要翻译： 具有三维存储器阵列的集成电路提供给定数量的存储器平面，但是可以通过省略与所省略的存储器平面相关联的掩模和处理步骤来替代地制造更少数量的存储器层，而不改变任何 用于其他存储器平面或其余器件的其他制造掩模，并且不需要对阵列的读取或读取/写入路径进行路由或其他配置更改。 用于选择性地启用某些层选择器电路的控制电路是可配置的，并且层选择器电路被适当地布置，以将实现的存储器层上的相应阵列线耦合到每个相应的I / O总线，而与所实现的存储器平面的数量无关。

公开(公告)号：US20080025088A1

公开(公告)日：2008-01-31

申请号：US11461343

申请日：2006-07-31

申请人： Roy E. Scheuerlein ,  Tyler J. Thorp ,  Luca G. Fasoli

发明人： Roy E. Scheuerlein ,  Tyler J. Thorp ,  Luca G. Fasoli

IPC分类号： G11C16/04

CPC分类号： G11C11/56 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/77

摘要： A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.

摘要翻译： 四级无源元件单元具有对应于降低电阻电平的存储器状态，其优选地分别映射到数据状态11,01,00和10. LSB和MSB优选地被映射为不同页面的一部分。 为了区分存储单元状态，对于参考电流电平和读取偏置电压的至少两种不同的组合来检测所选择的位线电流。 中间级参考用于读取LSB。 当读取MSB时，可以使用10和00数据状态之间的第一个参考，并且可以使用01和11数据状态之间的第二个参考，并且不需要使用中间级参考。 在某些实施例中，位线电流可以同时与第一和第二参考值进行比较，而不需要延迟来将位线电流稳定到不同的值，并且相应地生成MSB。

公开(公告)号：US20080025061A1

公开(公告)日：2008-01-31

申请号：US11461410

申请日：2006-07-31

申请人： Roy E. Scheuerlein ,  Christopher J. Petti

发明人： Roy E. Scheuerlein ,  Christopher J. Petti

IPC分类号： G11C17/00 ,  G11C11/00

CPC分类号： G11C8/06 ,  G11C5/145 ,  G11C5/147 ,  G11C7/12 ,  G11C8/08 ,  G11C8/12 ,  G11C11/5692 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0038 ,  G11C17/16 ,  G11C17/165 ,  G11C17/18 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74

摘要： A one-time field programmable (OTP) memory cell with related manufacturing and programming techniques is disclosed. An OTP memory cell in accordance with one embodiment includes at least one resistance change element in series with a steering element. The memory cell is field programmed using a reverse bias operation that can reduce leakage currents through the array as well as decrease voltage levels that driver circuitry must normally produce in program operations. An array of memory cells can be fabricated by switching the memory cells from their initial virgin state to a second resistance state during the manufacturing process. In one embodiment, the factory switching operation can include popping an anti-fuse of each memory cell to set them into the second resistance state. The array of memory cells in the second resistance state are provided to an end-user. Control circuitry is also provided with the memory array that can switch the resistance of selected cells back toward their initial resistance state to program the array in accordance with data received from a user or host device.

摘要翻译： 公开了具有相关制造和编程技术的一次性现场可编程（OTP）存储单元。 根据一个实施例的OTP存储器单元包括与转向元件串联的至少一个电阻变化元件。 使用反向偏置操作来对存储单元进行现场编程，该反向偏压操作可以减少通过阵列的漏电流，以及降低驱动器电路在程序运行中通常产生的电压电平。 可以通过在制造过程中将存储器单元从其初始状态切换到第二电阻状态来制造存储器单元阵列。 在一个实施例中，出厂切换操作可以包括弹出每个存储单元的反熔丝以使它们成为第二电阻状态。 将第二电阻状态的存储单元的阵列提供给终端用户。 控制电路还具有存储器阵列，其可以将所选择的单元的电阻切换回其初始电阻状态，以根据从用户或主机设备接收的数据对阵列进行编程。

公开(公告)号：US20080023790A1

公开(公告)日：2008-01-31

申请号：US11496874

申请日：2006-07-31

申请人： Roy E. Scheuerlein

发明人： Roy E. Scheuerlein

IPC分类号： H01L29/00 ,  G11C11/36

CPC分类号： H01L27/101 ,  G11C11/56 ,  G11C13/02 ,  G11C2211/5641 ,  G11C2213/33 ,  G11C2213/71 ,  H01L27/1021

摘要： A mixed-use memory array is disclosed. In one preferred embodiment, a memory array is provided comprising a first set of memory cells operating as one-time programmable memory cells and a second set of memory cells operating as rewritable memory cells. In another preferred embodiment, a memory array is provided comprising a first set of memory cells operating as memory cells that are programmed with a forward bias and a second set of memory cells operating as memory cells that are programmed with a reverse bias.

摘要翻译： 公开了一种混合存储器阵列。 在一个优选实施例中，提供存储器阵列，其包括作为一次性可编程存储器单元操作的第一组存储器单元和作为可重写存储器单元操作的第二组存储器单元。 在另一个优选实施例中，提供存储器阵列，其包括作为存储器单元操作的第一组存储器单元，所述存储器单元以正向偏置编程，而第二组存储器单元作为以反向偏置编程的存储器单元工作。

公开(公告)号：US07272052B2

公开(公告)日：2007-09-18

申请号：US11146952

申请日：2005-06-07

申请人： Roy E. Scheuerlein ,  Christopher J. Petti ,  Luca G. Fasoli

发明人： Roy E. Scheuerlein ,  Christopher J. Petti ,  Luca G. Fasoli

IPC分类号： G11C16/06

CPC分类号： G11C8/10 ,  G11C5/063 ,  G11C8/08 ,  G11C8/14

摘要： A decoding circuit for non-binary groups of memory line drivers is disclosed. In one embodiment, an integrated circuit is disclosed comprising a binary decoder and circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder. In another embodiment, an integrated circuit is disclosed comprising a memory array comprising a plurality of array lines, a non-integral-power-of-two number of array line driver circuits, and control circuitry configured to select one of the array line driver circuits. The control circuitry can comprise a binary decoder and a pre-decoder portion that performs a non-binary arithmetic operation. The concepts described herein may be used alone or in combination.

摘要翻译： 公开了一种用于非二进制组的存储器线驱动器的解码电路。 在一个实施例中，公开了一种集成电路，其包括二进制解码器和用于执行非二进制算术运算的电路，其中非二进制算术运算的结果被提供作为二进制解码器的输入。 在另一个实施例中，公开了一种集成电路，其包括存储器阵列，该存储器阵列包括多个阵列线，两个非整数倍数量的阵列线驱动器电路，以及控制电路，被配置为选择阵列线驱动电路之一 。 控制电路可以包括执行非二进制算术运算的二进制解码器和预解码器部分。 本文所述的概念可以单独使用或组合使用。

公开(公告)号：US07243203B2

公开(公告)日：2007-07-10

申请号：US10461295

申请日：2003-06-13

申请人： Roy E. Scheuerlein

发明人： Roy E. Scheuerlein

IPC分类号： G06F12/00

CPC分类号： G11C7/1039

摘要： The embodiments herein describe a memory device and method for reading and writing data. In one embodiment, a memory device is provided comprising a memory array and first and second data buffers in communication with the memory array. The second data buffer comprises a larger storage capacity than the first data buffer. During a write operation, data is stored in the second data buffer and then stored in the memory array. During a read operation, data is read from the memory array and then stored in the first data buffer but not in the second data buffer. Because the smaller-storage-capacity buffer takes less time to fill than the larger-storage-capacity buffer, there is less of a delay in outputting data from the memory device as compared to memory devices that use a larger-storage-capacity buffer for both read and write operations. Other embodiments are provided, and each of the embodiments can be used alone or in combination with one another.

摘要翻译： 本文的实施例描述了用于读取和写入数据的存储器件和方法。 在一个实施例中，提供了包括存储器阵列和与存储器阵列通信的第一和第二数据缓冲器的存储器件。 第二数据缓冲器包括比第一数据缓冲器更大的存储容量。 在写入操作期间，将数据存储在第二数据缓冲器中，然后存储在存储器阵列中。 在读操作期间，从存储器阵列中读取数据，然后存储在第一数据缓冲器中，而不存储在第二数据缓冲器中。 由于较小存储容量的缓冲器占用较大存储容量的缓冲区所需的时间较少，因此与使用较大存储容量缓冲区的存储器件相比，从存储器件输出数据的延迟较少 读写操作。 提供了其他实施例，并且每个实施例可以单独使用或彼此组合使用。