公开(公告)号：US08008669B2

公开(公告)日：2011-08-30

申请号：US12509892

申请日：2009-07-27

申请人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

发明人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

IPC分类号： H01L29/15

CPC分类号： H01L23/5252 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment an anti-fuse structure is provided that includes a first dielectric material having at least a first anti-fuse region and a second anti-fuse region, wherein at least one of the anti-fuse regions includes a conductive region embedded within the first dielectric material. The anti-fuse structure further includes a first diamond like carbon layer having a first conductivity located on at least the first dielectric material in the first anti-fuse region and a second diamond like carbon layer having a second conductivity located on at least the first dielectric material in the second anti-fuse region. In this embodiment, the second conductivity is different from the first conductivity and the first diamond like carbon layer and the second diamond like carbon layer have the same thickness. The anti-fuse structure also includes a second dielectric material located atop the first and second diamond like carbon layers. The second dielectric material includes at least one conductively filled region embedded therein.

摘要翻译： 在一个实施例中，提供了一种抗熔丝结构，其包括具有至少第一抗熔融区域和第二抗熔融区域的第一电介质材料，其中至少一个反熔丝区域包括嵌入在该熔断区域内的导电区域 第一电介质材料。 反熔丝结构还包括第一金刚石碳层，其具有位于第一抗熔融区域中的至少第一电介质材料上的第一导电性，第二类金刚石碳层具有位于至少第一电介质上的第二导电性 材料在第二个反熔丝区域。 在本实施例中，第二导电率不同于第一导电性，第一类金刚石碳层和第二类金刚石碳层具有相同的厚度。 反熔丝结构还包括位于第一和第二金刚石状碳层顶上的第二电介质材料。 第二电介质材料包括嵌入其中的至少一个导电填充区域。

公开(公告)号：US08003524B2

公开(公告)日：2011-08-23

申请号：US12177309

申请日：2008-07-22

申请人： Chih-Chao Yang ,  Simon Gaudet ,  Christian Lavoie ,  Shom Ponoth ,  Terry A. Spooner

发明人： Chih-Chao Yang ,  Simon Gaudet ,  Christian Lavoie ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.

摘要翻译： 提供一种互连结构，其包括具有增强的导电材料，优选Cu扩散性质的电镀种子层，其不需要使用单独的扩散和种子层。 具体地说，本发明提供了用于互连金属扩散增强的电镀种子层内的氧/氮过渡区域。 电镀种子层可以包括Ru，Ir或其合金，并且互连导电材料可以包括Cu，Al，AlCu，W，Ag，Au等。 优选地，互连导电材料是Cu或AlCu。 在更具体的术语中，本发明提供了单个接种层，其包括夹在顶部和底部种子区域之间的氧/氮过渡区域。 电镀种子层内的氧/氮过渡区的存在显着提高了电镀种子的扩散阻挡性。

公开(公告)号：US20110163450A1

公开(公告)日：2011-07-07

申请号：US12652485

申请日：2010-01-05

申请人： David V. Horak ,  Takeshi Nogami ,  Shom Ponoth ,  Chih-Chao Yang

发明人： David V. Horak ,  Takeshi Nogami ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/50 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating an integrated circuit comprising an electromigration barrier in a line of the integrated circuit includes forming a spacer; forming a segmented line adjacent to opposing sides of the spacer, the segmented line formed from a first conductive material; removing the spacer to form an empty line break; and filling the empty line break with a second conductive material to form an electromigration barrier that isolates electromigration effects within individual segments of the segmented line. An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.

摘要翻译： 一种用于制造集成电路的集成电路的方法，包括：集成电路的一行中的电迁移势垒包括形成间隔物; 形成与所述间隔物的相对侧相邻的分段线，所述分段线由第一导电材料形成; 移除间隔物以形成空线断裂; 并用第二导电材料填充空线断裂以形成电隔离屏蔽，其隔离分段线的各个段内的电迁移效应。 包括电迁移屏障的集成电路包括线，该线包括第一导电材料，该线还包括由一个或多个电迁移屏障隔开的多个线段，其中所述一个或多个电迁移屏障包括隔离的第二导电材料 线路各部分的电迁移效应。

公开(公告)号：US07892968B2

公开(公告)日：2011-02-22

申请号：US12017141

申请日：2008-01-21

申请人： Shyng-Tsong Chen ,  Steven J. Holmes ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Shyng-Tsong Chen ,  Steven J. Holmes ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/32139 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for via gouging and a related semiconductor structure are disclosed. In one embodiment, the method includes forming a via opening in a dielectric material, the via opening aligned with a conductor; forming a protective coating over the dielectric material and in the via opening; performing via gouging; and removing the protective coating over horizontal surfaces of the dielectric material. A semiconductor structure may include a via having an interface with a conductor, the interface including a three-dimensionally shaped region extending into and past a surface of the conductor, wherein an outer edge of the three-dimensionally shaped region is distanced from an outermost surface of the via.

摘要翻译： 公开了通孔沟槽的方法和相关的半导体结构。 在一个实施例中，该方法包括在电介质材料中形成通孔，通孔与导体对准; 在介电材料和通孔开口上形成保护涂层; 通过刨花进行; 并且在电介质材料的水平表面上去除保护涂层。 半导体结构可以包括与导体具有界面的通孔，所述界面包括延伸到导体表面中并经过导体表面的三维成形区域，其中三维成形区域的外边缘与最外表面 的通道。

公开(公告)号：US20100148366A1

公开(公告)日：2010-06-17

申请号：US12709928

申请日：2010-02-22

申请人： Chih-Chao Yang ,  Shom Ponoth

发明人： Chih-Chao Yang ,  Shom Ponoth

IPC分类号： H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the electromigration problem that is exhibited by prior art interconnect structures, are provided. In accordance with the present invention, a grain growth promotion layer, which promotes the formation of a conductive region within the interconnect structure that has a bamboo microstructure and an average grain size of larger than 0.05 microns is utilized. The inventive structure has improved performance and reliability.

摘要翻译： 提供了单镶嵌型或双镶嵌型的互连结构及其形成方法，其基本上减少了现有技术互连结构所呈现的电迁移问题。 根据本发明，利用促进在互连结构内形成具有竹微结构和平均粒径大于0.05微米的导电区域的晶粒生长促进层。 本发明的结构具有改进的性能和可靠性。

公开(公告)号：US07670497B2

公开(公告)日：2010-03-02

申请号：US11774041

申请日：2007-07-06

申请人： John A. Fitzsimmons ,  David L. Rath ,  Shom Ponoth ,  Michael Beck

发明人： John A. Fitzsimmons ,  David L. Rath ,  Shom Ponoth ,  Michael Beck

IPC分类号： H01B13/00

CPC分类号： C23G1/103 ,  H01L21/02063

摘要： A composition that may be used for cleaning a metal containing conductor layer, such as a copper containing conductor layer, within a microelectronic structure includes an aqueous acid, along with an oxidant material and a passivant material contained within the aqueous acid. The composition does not include an abrasive material. The composition is particularly useful for cleaning a residue from a copper containing conductor layer and an adjoining dielectric layer that provides an aperture for accessing the copper containing conductor layer within a microelectronic structure.

摘要翻译： 微电子结构中可用于清洗含金属导体层（例如含铜导电体层）的组合物包括酸水溶液以及氧化剂材料和含水酸性物质中的钝化材料。 组合物不包括研磨材料。 所述组合物特别可用于从含铜导体层和邻接的介电层清洁残留物，所述相邻介电层提供用于在微电子结构内进入含铜导体层的孔。

公开(公告)号：US20070166648A1

公开(公告)日：2007-07-19

申请号：US11306935

申请日：2006-01-17

申请人： Shom Ponoth ,  William America ,  Timothy Brunner ,  Ronald DellaGuardia ,  Kaushal Patel

发明人： Shom Ponoth ,  William America ,  Timothy Brunner ,  Ronald DellaGuardia ,  Kaushal Patel

IPC分类号： G03F7/26

CPC分类号： G03F7/0035 ,  H01L21/76811

摘要： A method and structure for an integrated via and line lithography followed by integrated via and line etch. A two-layered, negative resist based lithography is used to generate a dual damascene structure in the photoresist which is subsequently transferred into the underlying ILD using an lithography with an integrated RIE. A method is also provided to correct any misalignment between the via and trench during photolithography steps which would reduce the size of the via opening and impact the via resistance.

摘要翻译： 用于集成通孔和线光刻的方法和结构，随后是集成通孔和线蚀刻。 使用双层负性抗蚀剂基光刻法在光致抗蚀剂中产生双镶嵌结构，其随后使用具有集成RIE的光刻转移到下面的ILD中。 还提供了一种在光刻步骤期间校正通孔和沟槽之间的任何未对准的方法，这将减小通孔开口的尺寸并影响通孔电阻。

公开(公告)号：US20070117377A1

公开(公告)日：2007-05-24

申请号：US11286093

申请日：2005-11-23

申请人： Chih-Chao Yang ,  Shom Ponoth ,  David Rath ,  Keith Wong

发明人： Chih-Chao Yang ,  Shom Ponoth ,  David Rath ,  Keith Wong

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873 ,  H01L2221/1089

摘要： A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the sacrificial seed layer by reverse plating; and plating a conductive metal on the sacrificial seed layer in the patterned feature. Also provided is a dielectric layer having a via therein; a plating seed layer on the dielectric layer in the patterned feature; and a discontinuous sacrificial seed layer located in the patterned feature.

摘要翻译： 通过提供包括其中具有图案化特征的电介质层的结构来制造导体 - 电介质互连结构; 在所述图案化特征中的所述电介质层上沉积电镀种子层; 在通孔的电镀种子层上沉积牺牲种子层; 通过反向电镀减少牺牲种子层的厚度; 以及在所述图案化特征中的所述牺牲种子层上镀覆导电金属。 还提供了其中具有通孔的电介质层; 图案化特征中的电介质层上的电镀种子层; 以及位于图案化特征中的不连续牺牲种子层。

公开(公告)号：US20070117342A1

公开(公告)日：2007-05-24

申请号：US11164423

申请日：2005-11-22

申请人： Shyng-Tsong Chen ,  John Fitzsimmons ,  Shom Ponoth ,  Terry Spooner

发明人： Shyng-Tsong Chen ,  John Fitzsimmons ,  Shom Ponoth ,  Terry Spooner

IPC分类号： H01L21/76

CPC分类号： H01L21/32136 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/7684

摘要： A method comprises depositing a dielectric film layer, a hard mask layer, and a patterned photo resist layer on a substrate. The method further includes selectively etching the dielectric film layer to form sub-lithographic features by reactive ion etch processing and depositing a barrier metal layer and a copper layer. The method further includes etching the barrier metal layer and hard mask layer by gas cluster ion beam (GCIB) processing.

摘要翻译： 一种方法包括在衬底上沉积电介质膜层，硬掩模层和图案化光刻胶层。 该方法还包括通过反应离子蚀刻处理选择性地蚀刻电介质膜层以形成亚光刻特征，并沉积阻挡金属层和铜层。 该方法还包括通过气体簇离子束（GCIB）处理蚀刻阻挡金属层和硬掩模层。

公开(公告)号：US09768055B2

公开(公告)日：2017-09-19

申请号：US13590836

申请日：2012-08-21

申请人： Qing Liu ,  Nicolas Loubet ,  Prasanna Khare ,  Shom Ponoth ,  Maud Vinet ,  Bruce Doris

发明人： Qing Liu ,  Nicolas Loubet ,  Prasanna Khare ,  Shom Ponoth ,  Maud Vinet ,  Bruce Doris

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/76232 ,  H01L29/66772 ,  H01L29/78654

摘要： An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.