公开(公告)号：US10522226B2

公开(公告)日：2019-12-31

申请号：US16042972

申请日：2018-07-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  G06N3/08 ,  H01L27/11521 ,  H01L29/788

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.

公开(公告)号：US10515694B2

公开(公告)日：2019-12-24

申请号：US16148304

申请日：2018-10-01

Applicant: Silicon Storage Technology, Inc.

Inventor： Vipin Tiwari ,  Nhan Do ,  Hieu Van Tran

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10

Abstract: A method of reading a memory device having a plurality of memory cells by, and a device configured for, reading a first memory cell of the plurality of memory cells to generate a first read current, reading a second memory cell of the plurality of memory cells to generate a second read current, applying a first offset value to the second read current, and then combining the first and second read currents to form a third read current, and then determining a program state using the third read current. Alternately, a first voltage is generated from the first read current, a second voltage is generated from the second read current, whereby the offset value is applied to the second voltage, wherein the first and second voltages are combined to form a third voltage, and then the program state is determined using the third voltage.

公开(公告)号：US20190287631A1

公开(公告)日：2019-09-19

申请号：US15990220

申请日：2018-05-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30 ,  G06N3/08

Abstract: Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Various embodiments of a data drift detector suitable for detecting data drift in flash memory cells within the VMM array are disclosed.

公开(公告)号：US10388389B2

公开(公告)日：2019-08-20

申请号：US16271673

申请日：2019-02-08

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Xinjie Guo ,  Farnood Merrikh Bayat ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari

IPC: G11C16/14 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11558 ,  G11C7/18 ,  G11C8/14 ,  G11C16/04 ,  H01L29/788 ,  H01L27/11524

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

公开(公告)号：US20190244669A1

公开(公告)日：2019-08-08

申请号：US16387377

申请日：2019-04-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/14 ,  G11C16/0425 ,  G11C16/10

Abstract: A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.

公开(公告)号：US10311958B2

公开(公告)日：2019-06-04

申请号：US15593231

申请日：2017-05-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: H01L27/115 ,  G11C16/14 ,  G11C16/04 ,  G11C16/10

Abstract: A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.

公开(公告)号：US20190121556A1

公开(公告)日：2019-04-25

申请号：US16228313

申请日：2018-12-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G06F3/06 ,  G06F11/07 ,  G11C16/04 ,  H01L21/78 ,  H01L23/00 ,  H01L29/423 ,  G11C16/10 ,  H01L27/11521 ,  G11C16/26 ,  G11C16/08 ,  G11C16/34

Abstract: Multiple embodiments are disclosed for enhancing security and preventing hacking of a flash memory device. The embodiments prevent malicious actors from hacking a flash memory chip to obtain data that is stored within the chip. The embodiments include the use of fault detection circuits, address scrambling, dummy arrays, password protection, improved manufacturing techniques, and other mechanisms.

公开(公告)号：US10269432B2

公开(公告)日：2019-04-23

申请号：US15479235

申请日：2017-04-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/06 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32

Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.

公开(公告)号：US20190114097A1

公开(公告)日：2019-04-18

申请号：US15784025

申请日：2017-10-13

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G06F3/06 ,  G06F11/07 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34 ,  G11C16/10 ,  H01L29/423 ,  H01L23/00 ,  H01L21/78 ,  G11C16/04 ,  H01L27/11521

Abstract: Multiple embodiments are disclosed for enhancing security and preventing hacking of a flash memory device. The embodiments prevent malicious actors from hacking a flash memory chip to obtain data that is stored within the chip. The embodiments include the use of fault detection circuits, address scrambling, dummy arrays, password protection, improved manufacturing techniques, and other mechanisms.

公开(公告)号：US20180047454A1

公开(公告)日：2018-02-15

申请号：US15792590

申请日：2017-10-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen ,  Vipin Tiwari

IPC: G11C16/28 ,  G11C16/06 ,  G11C16/24 ,  G11C16/00

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C16/00 ,  G11C16/06 ,  G11C16/24 ,  G11C16/26 ,  G11C2207/063 ,  H01L27/11519

Abstract: Improved flash memory sensing circuits are disclosed. In one embodiment, a sensing circuit comprises a memory data read block, a memory reference block, a differential amplifier, and a precharge circuit. The precharge circuit compensates for parasitic capacitance between a bit line coupled to a selected memory cell and adjacent bit lines.