公开(公告)号：US09269829B2

公开(公告)日：2016-02-23

申请号：US14316864

申请日：2014-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L21/8238 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L29/42344 ,  H01L27/1157 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/792

Abstract: A method of manufacturing a semiconductor structure of a pair of split gate flash memory cells is provided. A pair of select gates spaced on a semiconductor substrate is formed, and a sacrificial spacer filling a central region between the select gates is formed. A charge trapping dielectric layer is formed conformally along sidewalls of the select gates and over top surfaces of the sacrificial spacer and the select gates, and a pair of memory gates corresponding to the pair of select gates is formed over and laterally abutting the charge trapping dielectric layer. The resulting semiconductor structure is also provided.

Abstract translation: 提供了一对制造分离栅闪存单元的半导体结构的方法。 形成在半导体衬底上间隔开的一对选择栅极，并且形成填充选择栅极之间的中心区域的牺牲隔离物。 电荷捕获电介质层沿着选择栅极的侧壁和牺牲间隔物和选择栅极的顶表面保形地形成，并且对应于该对选择栅极的一对存储栅极形成在电荷捕获电介质上方并横向邻接 层。 还提供所得的半导体结构。

公开(公告)号：US20160049420A1

公开(公告)日：2016-02-18

申请号：US14461565

申请日：2014-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L21/02601 ,  H01L21/02532 ,  H01L21/28273 ,  H01L21/3213 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7881

Abstract: Some embodiments relate to a memory device comprising a charge-trapping layer disposed between a control gate and a select gate. A capping structure is disposed over an upper surface of the control gate, and a composite spacer is disposed on a source-facing sidewall surface of the control gate. The capping structure and the composite spacer prevent damage to the control gate during one more etch processes used for contact formation to the memory device. To further limit or prevent the select gate sidewall etching, some embodiments provide for an additional liner oxide layer disposed along the drain-facing sidewall surface of the select gate. The liner oxide layer is configured as an etch stop layer to prevent etching of the select gate during the one or more etch processes. As a result, the one or more etch processes leave the control gate and select gate substantially intact.

Abstract translation: 一些实施例涉及包括设置在控制栅极和选择栅极之间的电荷捕获层的存储器件。 封盖结构设置在控制栅极的上表面上，并且复合间隔物设置在控制栅极的面向源的侧壁表面上。 封盖结构和复合间隔物在用于与存储器件的接触形成的一个以上蚀刻工艺期间防止对控制栅极的损坏。 为了进一步限制或防止选择栅极侧壁蚀刻，一些实施例提供沿着选择栅极的面向排水的侧壁表面设置的附加衬垫氧化物层。 衬里氧化物层被配置为蚀刻停止层，以防止在一个或多个蚀刻工艺期间蚀刻选择栅极。 结果，一个或多个蚀刻工艺离开控制栅极并基本上完整地选择栅极。

公开(公告)号：US20150069581A1

公开(公告)日：2015-03-12

申请号：US14023563

申请日：2013-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Ming Chang ,  Lee-Chuan Tseng ,  Shih-Wei Lin ,  Chih-Jen Chan ,  Yuan-Chih Hsieh ,  Ming Chyi Liu ,  Chung-Yen Chou

IPC: H01L21/265 ,  H01L29/06 ,  H01L29/02 ,  H01L21/3065

CPC classification number: H01L21/30655 ,  H01L21/2633 ,  H01L21/3065 ,  H01L27/00

Abstract: A method of etching a trench in a substrate is provided. The method repeatedly alternates between using a fluorine-based plasma to etch a trench, which has trench sidewalls, into a selected region of the substrate; and using a fluorocarbon plasma to deposit a liner on the trench sidewalls. The liner, when formed and subsequently etched, has an exposed sidewall surface that includes scalloped recesses. The trench, which includes the scalloped recesses, is then bombarded with a molecular beam where the molecules are directed on an axis parallel to the trench sidewalls to reduce the scalloped recesses.

Abstract translation: 提供了蚀刻衬底中的沟槽的方法。 该方法在使用氟基等离子体之间重复地交替，以将具有沟槽侧壁的沟槽蚀刻到衬底的选定区域中; 以及使用氟碳等离子体将衬垫沉积在沟槽侧壁上。 衬里当形成并随后被蚀刻时具有包括扇形凹槽的暴露的侧壁表面。 包括扇形凹槽的沟槽然后用分子束轰击，其中分子被引导在平行于沟槽侧壁的轴上以减少扇形凹部。