公开(公告)号：US20140216940A1

公开(公告)日：2014-08-07

申请号：US14127285

申请日：2011-06-24

申请人： Hui Wang ,  Yue Ma ,  Chuan He ,  Xi Wang

发明人： Hui Wang ,  Yue Ma ,  Chuan He ,  Xi Wang

IPC分类号： H01L21/02 ,  C25D21/10 ,  C25D17/00

CPC分类号： C25D21/10 ,  C25D5/08 ,  C25D5/18 ,  C25D5/20 ,  C25D7/12 ,  C25D7/123 ,  C25D17/00 ,  C25D17/001 ,  C25D17/002 ,  C25D17/008 ,  C25D17/06 ,  H01L21/02 ,  H01L21/67138

摘要： An apparatus for substrate metallization from electrolyte is provided. The apparatus comprises: an immersion cell containing metal salt electrolyte; at least one electrode connecting to at least one power supply; an electrically conductive substrate holder holding at least one substrate to expose a conductive side of the substrate to face the at least one electrode; an oscillating actuator for oscillating the substrate holder with an amplitude and a frequency; at least one ultrasonic device with an operating frequency and an intensity, disposed in the metallization apparatus; at least one ultrasonic power generator connecting to the ultrasonic device; at least one inlet for metal slat electrolyte feeding; and at least one outlet for metal salt electrolyte draining.

摘要翻译： 提供了一种用于从电解质进行衬底金属化的设备。 该装置包括：含有金属盐电解质的浸液池; 连接至少一个电源的至少一个电极; 保持至少一个基板的导电基板保持器，以暴露所述基板的导电侧面对所述至少一个电极; 用于以幅度和频率振荡衬底保持器的振荡致动器; 设置在所述金属化装置中的具有工作频率和强度的至少一个超声装置; 连接到所述超声波装置的至少一个超声波发生发电机; 用于金属板条电解质进料的至少一个入口; 和用于金属盐电解液排出的至少一个出口。

公开(公告)号：US08750127B2

公开(公告)日：2014-06-10

申请号：US12751656

申请日：2010-03-31

申请人： Qiong Zhang ,  Mohammad Masud Hasan ,  Xi Wang ,  Paparao Palacharla ,  Takao Naito ,  Fredrick S. Gruman

发明人： Qiong Zhang ,  Mohammad Masud Hasan ,  Xi Wang ,  Paparao Palacharla ,  Takao Naito ,  Fredrick S. Gruman

IPC分类号： H04L1/00 ,  H04L12/26 ,  H04L12/56

CPC分类号： H04L45/12 ,  H04L45/00 ,  H04L45/02 ,  H04L45/04 ,  H04L45/126 ,  H04L45/128 ,  H04L45/22 ,  H04L45/28

摘要： Systems and methods for multi-domain routing are provided. In some embodiments, a method for determining a path calculation from a source node to a destination node over a multi-domain network is provided. The method may include steps for receiving a predetermined sequence of domains for communicating information from the source node to the destination node, determining a link type for each of a plurality of links in the predetermined sequence of domains, modifying the link type of one or more of the plurality of links such that the plurality of links are unidirectional links towards a destination node, and determining a path along the predetermined sequence of domains based on the modified plurality of links.

摘要翻译： 提供了多域路由的系统和方法。 在一些实施例中，提供了一种用于确定通过多域网络从源节点到目的地节点的路径计算的方法。 该方法可以包括用于接收用于将信息从源节点传送到目的地节点的预定的域序列的步骤，为预定的域序列中的多个链路中的每一个确定链路类型，修改一个或多个链路类型 所述多个链路使得所述多个链路是朝向目的地节点的单向链路，以及基于所述修改的多个链路来确定沿着所述预定的域序列的路径。

公开(公告)号：US08681634B2

公开(公告)日：2014-03-25

申请号：US12751599

申请日：2010-03-31

申请人： Qiong Zhang ,  Mohammad Masud Hasan ,  Xi Wang ,  Paparao Palacharla ,  Takao Naito ,  Fredrick S. Gruman

发明人： Qiong Zhang ,  Mohammad Masud Hasan ,  Xi Wang ,  Paparao Palacharla ,  Takao Naito ,  Fredrick S. Gruman

IPC分类号： H04L12/26

CPC分类号： H04L45/04 ,  H04L45/128 ,  H04L45/22 ,  H04L45/24 ,  H04L45/28

摘要： Systems and methods for determining multiple paths in a multi-domain network are provided. In some embodiments, a method for determining multiple paths in a network is provided. The method may include determining a first path between a source node and a destination node and determining a second path disjoint from the first path. In some embodiments, to determine the second path includes determining which ingress nodes are available in a domain that includes the destination node, where the available ingress nodes are not part of the first path, and implementing a disjoint path algorithm for each of the available ingress nodes. To determine the first path includes implementing forward path calculations.

摘要翻译： 提供了用于确定多域网络中的多个路径的系统和方法。 在一些实施例中，提供了一种用于确定网络中的多个路径的方法。 该方法可以包括确定源节点和目的地节点之间的第一路径并确定与第一路径不相交的第二路径。 在一些实施例中，为了确定第二路径包括确定哪些入口节点在包括目的地节点的域中是可用的，其中可用入口节点不是第一路径的一部分，并且为每个可用入口实现不相交路径算法 节点。 确定第一条路径包括实现前向路径计算。

公开(公告)号：US08633090B2

公开(公告)日：2014-01-21

申请号：US13383416

申请日：2010-07-10

申请人： Xiang Wang ,  Xing Wei ,  Miao Zhang ,  Chenglu Lin ,  Xi Wang

发明人： Xiang Wang ,  Xing Wei ,  Miao Zhang ,  Chenglu Lin ,  Xi Wang

IPC分类号： H01L21/762

CPC分类号： H01L21/76256

摘要： A method for forming an edge-chamfered substrate with a buried insulating layer is provided, which comprises the following steps: providing a first substrate (S10); forming an etching mask layer on surfaces of the first substrate, wherein said etching mask layer is formed on the whole surfaces of the first substrate (S11); chamfering a glazed surface of the first substrate and the etching mask layer thereon by the edge grinding (S12); by rotary etching, etching the first substrate which is exposed by the edge grinding on the etching mask layer (S13); providing a second substrate (S14); and bonding the first substrate to the second substrate with a buried insulating layer (S15). The method avoids the edge collapses and the changes of the warp degree in subsequent processes.

摘要翻译： 提供一种形成具有掩埋绝缘层的边缘倒角衬底的方法，包括以下步骤：提供第一衬底（S10）; 在所述第一基板的表面上形成蚀刻掩模层，其中所述蚀刻掩模层形成在所述第一基板的整个表面上; 通过边缘磨削倒角第一基板的玻璃表面和其上的蚀刻掩模层（S12）; 通过旋转蚀刻，蚀刻通过边缘研磨而暴露在蚀刻掩模层上的第一衬底（S13）; 提供第二基板（S14）; 以及用掩埋绝缘层将第一衬底接合到第二衬底（S15）。 该方法避免了边缘崩溃和后续过程中翘曲度的变化。

公开(公告)号：US08559829B2

公开(公告)日：2013-10-15

申请号：US13176643

申请日：2011-07-05

申请人： Inwoong Kim ,  Paparao Palacharla ,  Xi Wang ,  Motoyoshi Sekiya

发明人： Inwoong Kim ,  Paparao Palacharla ,  Xi Wang ,  Motoyoshi Sekiya

IPC分类号： H04B10/06 ,  H04J14/00

CPC分类号： H04B10/6165 ,  H04B10/616 ,  H04L27/2697

摘要： In accordance with some embodiments of the present disclosure a method for receiving and processing an optical orthogonal frequency-division multiplexed signal containing a plurality of traffics comprises receiving the optical orthogonal frequency-division multiplexed signal. The method further comprises down-converting the optical orthogonal frequency-division multiplexed signal into the electrical domain to obtain an electrical signal; filtering the electrical signal to obtain a first portion of the electrical signal containing a first of the plurality of traffics and preprocessing the first portion of the electrical signal in a first parallel preprocessor; filtering the electrical signal to obtain a second portion of the electrical signal containing a second of the plurality of traffics and preprocessing the second portion of the electrical signal in a second parallel preprocessor; and combining the preprocessed first and second portions of the electrical signal to yield a combined electrical signal and demodulating the combined electrical signal.

摘要翻译： 根据本公开的一些实施例，用于接收和处理包含多个业务的光学正交频分复用信号的方法包括：接收光学正交频分复用信号。 该方法还包括将光正交频分多路复用信号下变频为电域以获得电信号; 过滤电信号以获得包含多个业务中的第一业务并且在第一并行预处理器中预处理电信号的第一部分的电信号的第一部分; 过滤电信号以获得包含多个业务中的第二业务的电信号的第二部分，并在第二并行预处理器中预处理电信号的第二部分; 以及组合电信号的预处理的第一和第二部分以产生组合的电信号并解调组合的电信号。

公开(公告)号：US08503789B2

公开(公告)日：2013-08-06

申请号：US12728656

申请日：2010-03-22

申请人： Wen-Yi Wu ,  Xi Wang

发明人： Wen-Yi Wu ,  Xi Wang

IPC分类号： G06K9/46 ,  G06K9/66

CPC分类号： G03B43/00

摘要： A system for measuring lens deflection of an electronic device includes a first shape, an image processing module, a first angle calculation module, and a second angle calculation module. The first shape is formed by edges of an ideal image captured that corresponds to a correctly mounted lens in the electronic device. The image processing module processes a currently captured image to acquire a second shape formed by edges of the present image. The first shape and the second shaped are imposed on each other. The first angle calculation module computes a first angle according to a rotation angle of the second shape relative to the first shape. A second angle calculation module computes a second angle according to a translating distance of the second shape relative to the first shape.

摘要翻译： 用于测量电子设备的透镜偏转的系统包括第一形状，图像处理模块，第一角度计算模块和第二角度计算模块。 第一形状由对应于电子设备中正确安装的透镜的理想图像的边缘形成。 图像处理模块处理当前拍摄的图像以获取由当前图像的边缘形成的第二形状。 第一形状和第二形状彼此施加。 第一角度计算模块根据第二形状相对于第一形状的旋转角度来计算第一角度。 第二角度计算模块根据第二形状相对于第一形状的平移距离来计算第二角度。

公开(公告)号：US20130152033A1

公开(公告)日：2013-06-13

申请号：US13696401

申请日：2011-09-23

申请人： Zhan Chai ,  Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Xi Wang

发明人： Zhan Chai ,  Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Xi Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5036 ,  H01L22/20

摘要： The present invention provides a Technology Computer Aided Design (TCAD) emulation calibration method of a Silicon On Insulator (SOI) field effect transistor, where process emulation Metal Oxide Semiconductor (MOS) device structures with different channel lengths Lgate are obtained by establishing a TCAD process emulation program; based on the process emulation MOS device structures, the process emulation MOS device structures are calibrated according to a Transmission Electron Microscope (TEM) test result, a secondary ion mass spectrometer (SIMS) test result, a Capacitor Voltage (CV) test result, a WAT test result, and a square resistance test result of an actual device, so as to complete TCAD emulation calibration of key electrical parameters of an SOI field effect transistor. Through the calibration method consistent with the present invention, in the same SOI process, TCAD emulation results of key parameters Vt and Idsat of MOSFETs of different sizes all meet a high-precision requirement that an error is less than 10%; moreover, accurate and effective pretest can be implement in the case of multiple splits, thereby providing effective guidance for research, development and optimization of a new process flow.

摘要翻译： 本发明提供了一种硅绝缘体（SOI）场效应晶体管的技术计算机辅助设计（TCAD）仿真校准方法，其中通过建立TCAD工艺获得具有不同沟道长度Lgate的工艺仿真金属氧化物半导体（MOS）器件结构 仿真程序; 基于过程仿真MOS器件结构，根据透射电子显微镜（TEM）测试结果，二次离子质谱仪（SIMS）测试结果，电容器电压（CV）测试结果， WAT测试结果和实际器件的方形电阻测试结果，以完成SOI场效应晶体管关键电参数的TCAD仿真校准。 通过与本发明一致的校准方法，在相同的SOI工艺中，不同尺寸的MOSFET的关键参数Vt和Idsat的TCAD仿真结果均满足误差小于10％的高精度要求; 此外，在多次拆分的情况下可以实现准确有效的预测试，从而为新工艺流程的研究，开发和优化提供有力的指导。

公开(公告)号：US08461651B2

公开(公告)日：2013-06-11

申请号：US13002303

申请日：2010-12-16

申请人： Xiaolu Huang ,  Xing Wei ,  Xinhong Cheng ,  Jing Chen ,  Miao Zhang ,  Xi Wang

发明人： Xiaolu Huang ,  Xing Wei ,  Xinhong Cheng ,  Jing Chen ,  Miao Zhang ,  Xi Wang

IPC分类号： H01L29/00

CPC分类号： H01L21/84 ,  H01L27/0255 ,  H01L27/1203

摘要： The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness.

摘要翻译： 本发明公开了一种SOI CMOS电路中的ESD保护结构。 ESD保护结构包括各种纵向（垂直）PN结结构，其具有用于电流的显着扩大的接合面积。 所得到的装置实现了增加的大电流释放能力。 还公开了制造ESD保护纵向PN结的品种的工艺。 所公开的制造工艺与当前SOI技术的兼容性降低了实施成本并提高了集成度。

公开(公告)号：US20130062696A1

公开(公告)日：2013-03-14

申请号：US13636128

申请日：2012-05-16

申请人： Zengfeng Di ,  Jiantao Bian ,  Miao Zhang ,  Xi Wang

发明人： Zengfeng Di ,  Jiantao Bian ,  Miao Zhang ,  Xi Wang

IPC分类号： H01L27/12 ,  H01L21/20 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L21/8258

摘要： The present invention provides an SOI semiconductor structure with a hybrid of coplanar germanium (Ge) and III-V, and a method for preparing the same. A heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material coplanar on an insulator includes at least one Ge substrate formed on the insulating layer, and the other substrate is a group III-V semiconductor material formed on the Ge semiconductor. The preparation method for forming the semiconductor structure includes: preparing a global Ge on insulator substrate structure; preparing a group III-V semiconductor material layer on the Ge on insulator substrate structure; performing photolithography and etching for the first time to make a patterned window to the above of a Ge layer to form a recess; preparing a spacer in the recess; preparing a Ge film by selective epitaxial growth; performing a chemical mechanical polishing to obtain the heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material being coplanar; removing the spacer and a defective Ge layer part close to the spacer; implementing isolation between Ge and the group III-V semiconductor material; and preparing a high-performance CMOS device including a Ge PMOS and a III-V NMOS by forming an MOS structure.

摘要翻译： 本发明提供具有共面锗（Ge）和III-V的杂化物的SOI半导体结构及其制备方法。 具有Ge和在绝缘体上共面的III-V族半导体材料的混合物的异质集成半导体结构包括形成在绝缘层上的至少一个Ge衬底，而另一衬底是形成在Ge上的III-V族半导体材料 半导体。 用于形成半导体结构的制备方法包括：制备全局Ge绝缘体衬底结构; 在Ge绝缘体衬底结构上制备III-V族III族半导体材料层; 第一次进行光刻和蚀刻，以形成图案化窗口到Ge层的上方以形成凹部; 在凹槽中制备间隔物; 通过选择性外延生长制备Ge膜; 进行化学机械抛光以获得具有Ge和III-V族半导体材料共面的混合物的异质集成半导体结构; 去除间隔物和靠近隔离物的缺陷Ge层部分; 实现Ge与III-V族III族半导体材料之间的隔离; 以及通过形成MOS结构来制备包括Ge PMOS和III-V NMOS的高性能CMOS器件。

公开(公告)号：US20130029478A1

公开(公告)日：2013-01-31

申请号：US13262656

申请日：2011-07-25

申请人： Miao Zhang ,  Bo Zhang ,  Zhongying Xue ,  Xi Wang

发明人： Miao Zhang ,  Bo Zhang ,  Zhongying Xue ,  Xi Wang

IPC分类号： H01L21/20

CPC分类号： H01L21/76251 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention discloses a method of fabricating high-mobility dual channel material based on SOI substrate, wherein compressive strained SiGe is epitaxially grown on a conventional SOI substrate to be used as channel material of PMOSFET; Si is then epitaixally grown on SiGe, and approaches such as ion implantation and annealing are employed to allow relaxation of part of strained SiGe and transfer strain to the Si layer thereon so as to form strained Si material as channel material of NMOSFET. With simple process and easy realization, this method can provide high-mobility channel material for NMOSFET and PMOSFET at the same time, well meeting the requirement of simultaneously enhancing the performance of NMOSFET and PMOSFET devices and therefore providing potential channel material for CMOS process of the next generation.

摘要翻译： 本发明公开了一种制造基于SOI衬底的高迁移率双通道材料的方法，其中压缩应变SiGe在常规SOI衬底上外延生长以用作PMOSFET的沟道材料; Si在SiGe上表面生长，采用离子注入和退火等方法，使部分应变SiGe弛豫并向其上的Si层转移应变，形成作为NMOSFET的沟道材料的应变Si材料。 通过简单的工艺和易于实现，该方法可以同时为NMOSFET和PMOSFET提供高迁移率沟道材料，可以很好地满足NMOSFET和PMOSFET器件同时提高性能的要求，从而为CMOS工艺提供潜在的沟道材料 下一代。