公开(公告)号：US20240220438A1

公开(公告)日：2024-07-04

申请号：US18090254

申请日：2022-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel Hsiuwei Loh ,  Todd David Basso

IPC: G06F13/40 ,  G06F1/08 ,  H01L23/538 ,  H01L25/065

CPC classification number: G06F13/4068 ,  G06F1/08 ,  H01L23/538 ,  H01L25/0655

Abstract: The disclosed semiconductor package includes a first chiplet area for receiving a first chiplet, a second chiplet area for receiving a second chiplet, and a host die coupled to the first and second chiplet areas. The semiconductor package also includes an interconnect directly coupling the first chiplet area to the second chiplet area. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240220415A1

公开(公告)日：2024-07-04

申请号：US18091140

申请日：2022-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Ganesh Balakrishnan ,  Kevin M. Lepak ,  Amit P. Apte

IPC: G06F12/0897

CPC classification number: G06F12/0897 ,  G06F2212/1016

Abstract: The disclosed computer-implemented method includes locating, from a processor storage, a partial tag corresponding to a memory request for a line stored in a memory having a tiered memory cache and in response to a partial tag hit for the memory request, locating, from a partition of the tiered memory cache indicated by the partial tag, a full tag for the line. The method also includes fetching, in response to a full tag hit, the requested line from the partition of the tiered memory cache. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240220379A1

公开(公告)日：2024-07-04

申请号：US18091163

申请日：2022-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G06F11/20 ,  G06F11/14

CPC classification number: G06F11/2094 ,  G06F11/1402 ,  G06F2201/805

Abstract: A memory controller includes a command queue, an arbiter, and a controller. The controller is responsive to a repair signal for migrating data from a failing region of a memory to a buffer, generating at least one command to perform a post-package repair operation of the failing region, and migrating the data from the buffer to a substitute region of the memory. The controller migrates the data to and from the buffer by providing migration read requests and migration write requests, respectively, to the command queue. The arbiter uses the plurality of arbitration rules for both the read migration requests and the write migration requests, and the read access requests and the write access requests.

公开(公告)号：US20240220315A1

公开(公告)日：2024-07-04

申请号：US18091443

申请日：2022-12-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Suchita Pati ,  Shaizeen Aga ,  Nuwan Jayasena ,  Matthew David Sinclair

IPC: G06F9/48 ,  G06F9/52

CPC classification number: G06F9/4881 ,  G06F9/52

Abstract: A processing system includes a scheduling mechanism for producing data for fine-grained reordering of workgroups of a kernel to produce blocks of data, such as for communication across devices to enable overlapping of a producer computation with an all-reduce communication across the network. This scheduling mechanism enables a first parallel processor to schedule and execute a set of workgroups of a producer operation to generate data for transmission to a second parallel processor in a desired traffic pattern. At the same time, the second parallel processor schedules and executes a different set of workgroups of the producer operation to generate data for transmission in a desired traffic pattern to a third parallel processor or back to the first parallel processor.

公开(公告)号：US20240220314A1

公开(公告)日：2024-07-04

申请号：US18091441

申请日：2022-12-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Harris Gasparakis

IPC: G06F9/48 ,  G06F9/52

CPC classification number: G06F9/4881 ,  G06F9/522

Abstract: A processing system flexibly schedules workgroups across kernels based on data dependencies between workgroups to enhance processing efficiency. The workgroups are partitioned into subsets based on the data dependencies and workgroups of a first subset that produces data are scheduled to execute immediately before workgroups of a second subset that consumes the data generated by the first subset. Thus, the processing system does not execute one kernel at a time, but instead schedules workgroups across kernels based on data dependencies across kernels. By limiting the sizes of the subsets to the amount of data that can be stored at local caches, the processing system increases the probability that data to be consumed by workgroups of a subset will be resident in a local cache and will not require a memory access.

公开(公告)号：US20240220296A1

公开(公告)日：2024-07-04

申请号：US18090605

申请日：2022-12-29

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： Philip Ng ,  Nippon Raval ,  Jeremy W. Powell ,  Donald Matthews, JR. ,  David Kaplan

IPC: G06F9/455 ,  G06F12/1081

CPC classification number: G06F9/45558 ,  G06F12/1081 ,  G06F2009/45587

Abstract: A processor manages memory-mapped input/output (MMIO) accesses, in secure fashion, at an input/output memory management unit (IOMMU). The processor is configured to ensure that, for a given MMIO request issued by a processor core and associated with a particular executing VM, the request is targeted to a MMIO address that has been assigned to the VM by a security module (e.g., a security co-processor). The processor thus prevents a malicious entity from accessing confidential information of a VM via MMIO requests.

公开(公告)号：US20240220108A1

公开(公告)日：2024-07-04

申请号：US18147963

申请日：2022-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Jayesh Hari Joshi ,  Alicia Wen Ju Yurie Leong ,  William Robert Alverson ,  Joshua Taylor Knight ,  Jerry Anton Ahrens ,  Grant Evan Ley ,  Amitabh Mehra ,  Anil Harwani

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0653 ,  G06F3/0673

Abstract: Automated memory overclocking is described. In accordance with the described techniques, one or more sets of overclocked memory settings of a memory are automatically selected for performance testing and stability testing of the memory. The one or more sets of the overclocked memory settings are tested for performance of the memory and a performance indication is output for each of the one or more sets of the overclocked memory settings. The one or more sets of the overclocked memory settings are tested for stability of the memory and a stability indication is output for each of the one or more sets of the overclocked memory settings. One of the one or more sets of the overclocked memory settings are selected as optimized overclocked memory settings for the memory.

公开(公告)号：US12028190B1

公开(公告)日：2024-07-02

申请号：US18086960

申请日：2022-12-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Pradeep Jayaraman ,  Karthik Gopalakrishnan ,  Andrew Egli

IPC: H04L25/03 ,  H04L25/49

CPC classification number: H04L25/03038 ,  H04L25/4917 ,  H04L2025/03471

Abstract: A driver circuit includes a feed-forward equalization (FFE) circuit. The FFE circuit receives a plurality of pulse-amplitude modulation (PAM) symbol values to be transmitted at one of multiple PAM levels. The FFE circuit includes a first partial lookup table, one or more additional partial lookup tables, and an adder circuit. The first partial lookup table contains partial finite impulse-response (FIR) values and indexed based on a current PAM symbol value, a precursor PAM symbol value, and a postcursor PAM symbol value. The one or more additional partial lookup tables each contain partial FIR values and indexed based on a respective additional one or more of the PAM symbol values. The adder circuit adds results of lookups from the first partial lookup table and the additional partial lookup tables to produce an output value.

公开(公告)号：US20240212777A1

公开(公告)日：2024-06-27

申请号：US18146558

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Robin Conradine Knauerhase

IPC: G11C29/14

CPC classification number: G11C29/14 ,  G11C2029/1208

Abstract: Memory verification using processing-in-memory is described. In accordance with the described techniques, memory testing logic is loaded into a processing-in-memory component. The processing-in-memory component executes the memory testing logic to test a memory. An indication is output of a detected fault in the memory based on testing the memory.

公开(公告)号：US20240211134A1

公开(公告)日：2024-06-27

申请号：US18087964

申请日：2022-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Karthik Ramu Sangaiah ,  Anthony Thomas Gutierrez

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory controller includes an arbiter, a vector arithmetic logic unit (VALU), a read buffer and a write buffer both coupled to the VALU, and an atomic memory operation scheduler. The VALU performs scattered atomic memory operations on arrays of data elements responsive to selected memory access commands. The atomic memory operation scheduler is for scheduling atomic memory operations at the VALU; identifying a plurality of scattered atomic memory operations with commutative and associative properties, the plurality of scattered atomic memory operations on at least one element of an array of data elements associated with an address; and commanding the VALU to perform the plurality of scattered atomic memory operations.