公开(公告)号：US4835420A

公开(公告)日：1989-05-30

申请号：US121612

申请日：1987-11-17

Applicant: David S. Rosky

Inventor： David S. Rosky

IPC: H03K19/013 ,  H03K19/018

CPC classification number: H03K19/0136 ,  H03K19/01812

Abstract: A method and apparatus for converting input signals at one predetermined logic level to output signals at corresponding different logic levels includes differential amplification of input signals with a first output of a differential amplifier connected for establishing a voltage level between voltage limits V.sub.cc and V.sub.ee at the output of an output driver in response to variations in amplifier output. A pull-down transistor has a collector connected to the output driver output, an emitter connected to the V.sub.ee voltage source, and a base capacitively coupled to the second amplifier output. In further aspects of the invention, a voltage clamp embracing a transistor with a base connected to receive a predetermined control voltage has an emitter connected to the pull-down transistor base and a collector connected to the V.sub.cc voltage source.

Abstract translation: 用于将输入信号以一个预定逻辑电平转换为在相应不同逻辑电平输出信号的方法和装置包括输入信号的差分放大，其中连接的差分放大器的第一输出用于在输出端处建立电压极限Vcc和Vee之间的电压电平 的输出驱动器，以响应放大器输出的变化。 下拉晶体管具有连接到输出驱动器输出的集电极，连接到Vee电压源的发射极和与第二放大器输出电容耦合的基极。 在本发明的另外的方面，包含具有连接以接收预定控制电压的基极的晶体管的电压钳具有连接到下拉晶体管基极的发射极和连接到Vcc电压源的集电极。

公开(公告)号：US09590756B2

公开(公告)日：2017-03-07

申请号：US14027518

申请日：2013-09-16

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Francesco Caggioni ,  Dimitrios Giannakopoulos

IPC: H04J14/08 ,  H04J3/16 ,  H04L12/26

CPC classification number: H04J3/1664

Abstract: Various aspects provide for mapping a plurality of signals to generate a combined signal. An aggregation component is configured for generating a combined signal that comprises a higher data rate than a data rate associated with a plurality of signals based on mapped data associated with the plurality of signals. The aggregation component comprises a mapper component. The mapper component is configured for generating the mapped data based on a mapping distribution pattern associated with a generic mapping procedure. In an aspect, a de-aggregation component is configured for recovering the plurality of signals from a pseudo signal transmitted at a data rate of the combined signal. In another aspect, the de-aggregation component comprises a de-mapper component configured for de-mapping the mapped data based on the mapping distribution pattern associated with the generic mapping procedure.

Abstract translation: 各种方面提供用于映射多个信号以生成组合信号。 聚合组件被配置为基于与多个信号相关联的映射数据来生成包括比与多个信号相关联的数据速率更高的数据速率的组合信号。 聚合组件包括映射器组件。 映射器组件被配置用于基于与通用映射过程相关联的映射分布模式来生成映射数据。 在一方面，解聚合组件被配置为从以组合信号的数据速率发送的伪信号中恢复多个信号。 在另一方面，解聚合组件包括解映射器组件，其被配置为基于与通用映射过程相关联的映射分布模式来对映射的数据进行解映射。

公开(公告)号：US09568511B2

公开(公告)日：2017-02-14

申请号：US14208408

申请日：2014-03-13

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Luca Ravezzi ,  Qawi Harvard ,  Hamid Partovi

IPC: G01R19/165 ,  G01R19/00 ,  G06F1/26

CPC classification number: G01R19/16552 ,  G01R19/0007 ,  G06F1/26 ,  G06F1/305

Abstract: Various aspects provide a high frequency voltage supply monitor capable of monitoring high frequency variations of the voltage supply inside a microelectronic circuit substantially in real time. The voltage supply monitor can comprise a differential amplifier circuit having a substantially constant gain over a wide bandwidth, allowing the supply voltage variations to be amplified according to a known gain under a wide range of conditions. The amplified signal can then be sent to an output port for monitoring and measurement by an external display device.

Abstract translation: 各种方面提供了一种能够基本上实时地监测微电子电路内的电压供应的高频变化的高频电压监视器。 电压监视器可以包括在宽带宽上具有基本上恒定的增益的差分放大器电路，从而允许根据在宽范围条件下的已知增益放大电源电压变化。 放大的信号然后可以被发送到输出端口，用于由外部显示装置进行监视和测量。

公开(公告)号：US09558012B2

公开(公告)日：2017-01-31

申请号：US13772498

申请日：2013-02-21

Applicant: Keyur Chudgar ,  Kumar Sankaran

Inventor： Keyur Chudgar ,  Kumar Sankaran

IPC: G06F9/00 ,  G06F15/177 ,  G06F9/44

CPC classification number: G06F9/4408 ,  G06F9/4401 ,  G06F9/4406 ,  G06F9/4416

Abstract: Various aspects of the present disclosure provide for a system that is able to boot from a variety of media that can be connected to the system, including SPI NOR and SPI NAND memory, universal serial bus (“USB”) devices, and devices attached via PCIe and Ethernet interfaces. When the system is powered on, the system processor is held in a reset mode, while a microcontroller in the system identifies an external device to be booted, and then copies a portion of boot code from the external device to an on-chip memory. The microcontroller can then direct the reset vector to the boot code in the on-chip memory and brings the system processor out of reset. The system processor can execute the boot code in-place on the on-chip memory, which initiates the system memory and the second stage boot loader.

Abstract translation: 本公开的各个方面提供了能够从可以连接到系统的各种媒体引导的系统，包括SPI NOR和SPI NAND存储器，通用串行总线（“USB”）设备，以及经由 PCIe和以太网接口。 当系统通电时，系统处理器保持在复位模式，而系统中的微控制器识别要引导的外部设备，然后将一部分引导代码从外部设备复制到片上存储器。 然后，微控制器可以将复位向量引导到片上存储器中的引导代码，并使系统处理器不复位。 系统处理器可以在片上存储器上就地执行启动代码，从而启动系统内存和第二级引导加载程序。

公开(公告)号：US09344209B2

公开(公告)日：2016-05-17

申请号：US14016534

申请日：2013-09-03

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Stacy Nichols ,  Sameer Gandhi ,  Burt Christian

IPC: H04J3/06

CPC classification number: H04J3/0697 ,  H04J3/0661

Abstract: Discrete time compensation mechanisms include a channel component configured for determining which channel of a plurality of channels to process time slots of sampled data that are time stamped in a discrete time and processing the time slots of the sampled data to the plurality of channels. A common channel clock component is configured for time stamping the time slots of the sampled data in the discrete time domain that is faster than a non-discrete reference time stamp of continuous data from which the time slots are sampled from and for processing the sampled data through the plurality of channels faster than the continuous data is being received. Compensations for one or more gaps are generated based on a set of predetermined criteria and a corrected time stamp is applied to the sampled data for processing among different processing channels.

Abstract translation: 离散时间补偿机制包括被配置用于确定多个信道的哪个信道处理在离散时间中被时间戳的采样数据的时隙并且将采样数据的时隙处理到多个信道的信道分量。 公共通道时钟部件被配置用于对离散时域中的采样数据的时隙进行时间戳，该时隙比连续数据的非离散参考时间戳更快，从该数据的时隙中抽取时隙并从处理采样数据 通过多个信道比正在接收的连续数据更快。 基于一组预定标准产生一个或多个间隙的补偿，并且将校正的时间戳应用于采样数据，以在不同的处理通道之间进行处理。

公开(公告)号：US09325287B2

公开(公告)日：2016-04-26

申请号：US14162896

申请日：2014-01-24

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Nanda Govind Jayaraman ,  Tarun Gupta

IPC: H03F3/45 ,  H03G3/30

CPC classification number: H03G3/30 ,  H03G1/0029

Abstract: Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the resistor. On applying a control voltage to the third transistor and applying an input voltage to the first control port, the second control port is selectively modified by the control voltage to produce a desired output at the first input port and the second input port.

Abstract translation: 提供了一种可编程增益放大器，其包括可实时动态地控制输出电压的受控增益步长。 可编程增益放大器包括第一晶体管和第二晶体管，其包括相应的控制端口，输入端口和输出端口。 可编程增益放大器还包括连接到晶体管的输出端口的电阻器。 此外，至少第三晶体管与电阻器并联连接到输出端口。 在对第三晶体管施加控制电压并向第一控制端口施加输入电压时，通过控制电压选择性地修改第二控制端口，以在第一输入端口和第二输入端口产生期望的输出。

公开(公告)号：US09213643B2

公开(公告)日：2015-12-15

申请号：US13799268

申请日：2013-03-13

Applicant: David Alan Kruckemyer ,  John Gregory Favor

Inventor： David Alan Kruckemyer ,  John Gregory Favor

IPC: G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G06F1/32

CPC classification number: G06F12/0833 ,  G06F1/3243 ,  G06F2212/1028 ,  Y02D10/13

Abstract: Various aspects provide for implementing a cache coherence protocol. A system comprises at least one processing component and a centralized controller. The at least one processing component comprises a cache controller. The cache controller is configured to manage a cache memory associated with a processor. The centralized controller is configured to communicate with the cache controller based on a power state of the processor.

Abstract translation: 各个方面提供了实现高速缓存一致性协议。 系统包括至少一个处理部件和集中控制器。 所述至少一个处理组件包括高速缓存控制器。 高速缓存控制器被配置为管理与处理器相关联的高速缓冲存储器。 集中控制器被配置为基于处理器的功率状态与高速缓存控制器进行通信。

公开(公告)号：US20150323569A1

公开(公告)日：2015-11-12

申请号：US14208408

申请日：2014-03-13

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Luca Ravezzi ,  Qawi Harvard ,  Hamid Partovi

IPC: G01R19/00

CPC classification number: G01R19/16552 ,  G01R19/0007 ,  G06F1/26 ,  G06F1/305

Abstract: Various aspects provide a high frequency voltage supply monitor capable of monitoring high frequency variations of the voltage supply inside a microelectronic circuit substantially in real time. The voltage supply monitor can comprise a differential amplifier circuit having a substantially constant gain over a wide bandwidth, allowing the supply voltage variations to be amplified according to a known gain under a wide range of conditions. The amplified signal can then be sent to an output port for monitoring and measurement by an external display device.

Abstract translation: 各种方面提供了一种能够基本上实时地监测微电子电路内的电压供应的高频变化的高频电压监视器。 电压监视器可以包括在宽带宽上具有基本上恒定的增益的差分放大器电路，从而允许根据在宽范围条件下的已知增益放大电源电压变化。 放大的信号然后可以被发送到输出端口，用于由外部显示装置进行监视和测量。

公开(公告)号：US09170642B2

公开(公告)日：2015-10-27

申请号：US13848377

申请日：2013-03-21

Applicant: Kjeld P. Svendsen ,  Arun Jangity

Inventor： Kjeld P. Svendsen ,  Arun Jangity

IPC: G06F1/00 ,  G06F1/04 ,  G06F1/26 ,  G06F1/32 ,  H03L3/00

CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  H03L3/00 ,  Y02D10/126 ,  Y02D10/172

Abstract: Systems and methods are provided that facilitate power management in a processing device. The system contains a power management component and a coupled to the processing device. The power management component determines and input rate and target voltages and/or frequency. The power management component can scale voltages and/or frequencies based on target voltages and/or frequencies. Accordingly, power consumption can be reduced and processing devices can be more efficient.

Abstract translation: 提供了便于处理设备中的电源管理的系统和方法。 该系统包含电源管理组件，并耦合到处理设备。 电源管理组件确定和输入速率和目标电压和/或频率。 电源管理组件可以基于目标电压和/或频率来缩放电压和/或频率。 因此，可以降低功耗，并且处理装置可以更有效率。

公开(公告)号：US09158713B1

公开(公告)日：2015-10-13

申请号：US12772832

申请日：2010-05-03

Applicant: Keyur Chudgar ,  Vinay Ravuri ,  Loc Nhin Ho

Inventor： Keyur Chudgar ,  Vinay Ravuri ,  Loc Nhin Ho

IPC: G06F9/46 ,  G06F13/00 ,  G06F9/50 ,  G06F13/28

CPC classification number: G06F13/00 ,  G06F9/5083 ,  G06F13/28 ,  G06F2213/0038 ,  Y02D10/14

Abstract: A system and method are provided for evenly distributing central processing unit (CPU) packet processing workloads. The method accepts packets for processing at a port hardware module port interface. The port hardware module supplies the packets to a direct memory access (DMA) engine for storage in system memory. The port hardware module also supplies descriptors to a mailbox. Each descriptor identifies a corresponding packet. The mailbox has a plurality of slots, and loads the descriptors into empty slots. There is a plurality of CPUs, and each CPU fetches descriptors from assigned slots in the mailbox. Then, each CPU processes packets in the system memory in the order in which the associated descriptors are fetched. A load balancing module estimates each CPU workload and reassigns mailbox slots to CPUs in response to unequal CPU workloads.

Abstract translation: 提供了一种用于均匀分布中央处理单元（CPU）数据包处理工作负载的系统和方法。 该方法接受在端口硬件模块端口接口处理的数据包。 端口硬件模块将数据包提供给直接存储器访问（DMA）引擎，用于存储在系统内存中。 端口硬件模块还向邮箱提供描述符。 每个描述符标识相应的数据包。 邮箱有多个插槽，并将描述符加载到空插槽中。 有多个CPU，每个CPU从邮箱中分配的插槽中提取描述符。 然后，每个CPU按照相关联的描述符获取的顺序处理系统内存中的数据包。 负载平衡模块估计每个CPU工作负载，并将邮箱插槽重新分配给CPU，以响应不平等的CPU工作负载。