公开(公告)号：US20090011564A1

公开(公告)日：2009-01-08

申请号：US11902460

申请日：2007-09-21

申请人： Min-Liang Chen

发明人： Min-Liang Chen

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/76237

摘要： A nitrogen implantation to a substrate on the edges of an active area is added before filling an insulating layer in a trench during a shallow trench isolation process to reduce the thickness of a gate oxide formed later on the edges of the active area.

摘要翻译： 在浅沟槽隔离工艺期间，在填充沟槽中的绝缘层之前，加入到有源区边缘上的衬底的氮注入，以减少稍后在有源区的边缘上形成的栅极氧化物的厚度。

公开(公告)号：US20090010047A1

公开(公告)日：2009-01-08

申请号：US11957044

申请日：2007-12-14

申请人： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

发明人： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

IPC分类号： G11C11/56

CPC分类号： G11C13/0061 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

摘要： A phase change memory writing circuit is provided. The circuit comprises a writing path and a fast write control unit. The writing path further comprises a current driving unit, a first switch device and a phase change memory cell. The current driving unit is coupled to a high voltage source and outputs a driving current. The first switch device is controlled by a first control signal. The fast write control unit is coupled to the writing path to provide a writing voltage to the writing path. When the first switch device is turned off, the fast write control unit outputs the writing voltage to the writing path. When the first switch device is turned on, the fast write control unit stops outputting the writing voltage to the writing path.

摘要翻译： 提供了相变存储器写入电路。 该电路包括写入路径和快速写入控制单元。 写入路径还包括电流驱动单元，第一开关器件和相变存储器单元。 电流驱动单元耦合到高电压源并输出驱动电流。 第一开关装置由第一控制信号控制。 快速写入控制单元耦合到写入路径以向写入路径提供写入电压。 当第一开关装置关闭时，快速写入控制单元将写入电压输出到写入路径。 当第一开关装置接通时，快速写入控制单元停止向写入路径输出写入电压。

公开(公告)号：US20080316674A1

公开(公告)日：2008-12-25

申请号：US12000145

申请日：2007-12-10

申请人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

发明人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

IPC分类号： H01G4/06 ,  H01G9/00

CPC分类号： H01L28/91 ,  H01G4/252 ,  H01G4/33 ,  H01L27/10852

摘要： Capacitors and methods for fabricating the same are provided. An exemplary embodiment of a capacitor comprises a dielectric layer and a first conductive layer thereover. A supporting rib is embedded in the first conductive layer and extends along a first direction. A second conductive layer is embedded in the first conductive layer and extends along a second direction perpendicular with the first direction, wherein a portion of the second conductive layer forms across the supporting rib and is structurally supported by the supporting rib. A capacitor layer is formed between the first and second conductive layers to electrically insulate the first and second conductive layers.

摘要翻译： 提供了电容器及其制造方法。 电容器的示例性实施例包括电介质层和其上的第一导电层。 支撑肋嵌入在第一导电层中并且沿着第一方向延伸。 第二导电层被嵌入在第一导电层中并且沿着与第一方向垂直的第二方向延伸，其中第二导电层的一部分跨过支撑肋形成并且在结构上由支撑肋支撑。 在第一和第二导电层之间形成电容器层，以使第一和第二导电层电绝缘。

公开(公告)号：US20080311715A1

公开(公告)日：2008-12-18

申请号：US12068617

申请日：2008-02-08

申请人： Po-Kang Hu ,  Cheng-Che Lee ,  Ta-Wei Tung ,  Meng-Cheng Chen

发明人： Po-Kang Hu ,  Cheng-Che Lee ,  Ta-Wei Tung ,  Meng-Cheng Chen

IPC分类号： H01L21/8236

CPC分类号： H01L29/4236 ,  H01L21/2252 ,  H01L27/10876 ,  H01L29/105 ,  H01L29/66621

摘要： A method for forming a semiconductor device is disclosed. A substrate comprising trenches are provided. Dopants are doped into a region of the substrate neighboring a sidewall of the trenches by using an isotropic doping method. A gate dielectric layer is formed on the sidewall of the substrate. A gate electrode is formed in the trenches, wherein the gate electrode protrudes a surface of the substrate.

摘要翻译： 公开了一种用于形成半导体器件的方法。 提供了包括沟槽的衬底。 通过使用各向同性掺杂方法将掺杂剂掺杂到与沟槽的侧壁相邻的衬底的区域中。 栅介质层形成在衬底的侧壁上。 在沟槽中形成栅电极，其中栅电极突出基片的表面。

公开(公告)号：US20080305594A1

公开(公告)日：2008-12-11

申请号：US11828344

申请日：2007-07-25

申请人： Chung-We Pan ,  Shou-Yu Chang ,  Tzeng-Wen Tzeng ,  Ching-Hung Fu ,  Chih-Ping Chung

发明人： Chung-We Pan ,  Shou-Yu Chang ,  Tzeng-Wen Tzeng ,  Ching-Hung Fu ,  Chih-Ping Chung

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/11521 ,  H01L27/11524

摘要： A method for fabricating a non-volatile memory is provided. Parallel-arranged isolation structures are disposed in a substrate and protrude from the surface of the substrate to define active regions. Mask layers intersecting the isolation structures are deposited on the substrate. The surface of the mask layers is higher than that of the isolation structures. Doped regions are formed in the substrate. Insulating layers are deposited on the substrate between the mask layers. The insulating layers and the mask layers have different etch selectivities. The mask layers are removed to expose the substrate. A tunneling dielectric layer is formed on the substrate. A floating gate is deposited on the substrate surrounded by the isolation structures and the insulating layers. The surface of the floating gate is lower than that of the isolation structures. An inter-gate dielectric layer is deposited on the substrate. A control gate is disposed between the insulating layers.

摘要翻译： 提供了一种用于制造非易失性存储器的方法。 平行布置的隔离结构设置在基板中并且从基板的表面突出以限定有源区。 与隔离结构相交的掩模层沉积在基板上。 掩模层的表面高于隔离结构的表面。 在衬底中形成掺杂区域。 绝缘层沉积在掩模层之间的衬底上。 绝缘层和掩模层具有不同的蚀刻选择性。 去除掩模层以露出基底。 在衬底上形成隧道介电层。 浮置栅极沉积在由隔离结构和绝缘层围绕的基板上。 浮动栅极的表面比隔离结构的表面低。 在衬底上沉积栅极间电介质层。 控制栅极设置在绝缘层之间。

公开(公告)号：US07462545B2

公开(公告)日：2008-12-09

申请号：US11162727

申请日：2005-09-21

申请人： Jih-Wen Chou ,  Chih-Hsun Chu

发明人： Jih-Wen Chou ,  Chih-Hsun Chu

IPC分类号： H01L21/336

CPC分类号： H01L29/0653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device is provided. The semiconductor device has a gate structure, a source region, a drain region, and a pair of dielectric barrier layers. The gate structure is formed on a substrate. The source region and the drain region are formed in the substrate next to the gate structure, and a channel region is formed between the source region and the drain region underneath the gate structure. The pair of dielectric barrier layers is respectively formed in the substrate underneath the gate structure between the source region and the drain region. The dielectric barrier layers are used for reducing the drain induced barrier lowering effect in a nanometer scale device.

摘要翻译： 提供半导体器件。 半导体器件具有栅极结构，源极区，漏极区和一对介电阻挡层。 栅极结构形成在基板上。 源极区域和漏极区域形成在栅极结构旁边的衬底中，并且在栅极结构之下的源极区域和漏极区域之间形成沟道区域。 一对电介质阻挡层分别形成在源极区域和漏极区域之间的栅极结构下方的衬底中。 电介质阻挡层用于在纳米级装置中降低漏极引发的阻挡层降低效果。

公开(公告)号：US20080296552A1

公开(公告)日：2008-12-04

申请号：US12106822

申请日：2008-04-21

申请人： Hong-Hui Hsu

发明人： Hong-Hui Hsu

IPC分类号： H01L47/00 ,  H01L21/00

CPC分类号： H01L45/1675 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

摘要： Phase change memory cell structures and methods for fabricating the same are provided. An exemplary embodiment of a phase change memory cell structure includes a first electrode formed over a first dielectric layer. A second dielectric layer is formed over the first electrode. A conductive member is formed through the second dielectric layer and electrically contacting the first electrode, wherein the conductive member comprises a lower element and an upper element sequentially stacking over the first electrode, and the lower and upper elements comprises different materials. A phase change material layer is formed over the second dielectric layer, electrically contacting the conductive member. A second electrode is formed over the phase change material layer.

摘要翻译： 提供了相变存储单元结构及其制造方法。 相变存储单元结构的示例性实施例包括形成在第一介电层上的第一电极。 在第一电极上形成第二电介质层。 导电构件通过第二电介质层形成并与第一电极电接触，其中导电构件包括顺序地堆叠在第一电极上的下部元件和上部元件，并且下部和上部元件包括不同的材料。 在第二电介质层上形成相变材料层，与导电构件电接触。 在相变材料层上形成第二电极。

公开(公告)号：US20080293213A1

公开(公告)日：2008-11-27

申请号：US11774811

申请日：2007-07-09

申请人： Neng Hui Yang ,  Hai Jun Zhao

发明人： Neng Hui Yang ,  Hai Jun Zhao

IPC分类号： H01L21/76

CPC分类号： H01L21/76237 ,  H01L21/76235

摘要： A method for preparing a shallow trench isolation comprising the steps of forming at least one trench in a semiconductor substrate, performing an implanting process to implant nitrogen-containing dopants into an upper sidewall of the trench such that the concentration of the nitrogen-containing dopants in the upper sidewall is higher than that in the bottom sidewall of the trench, forming a spin-on dielectric layer filling the trench and covering the surface of the semiconductor substrate, performing a thermal oxidation process to form a silicon oxide layer covering the inner sidewall. Since the nitrogen-containing dopants can inhibit the oxidation rate and the concentration of the nitrogen-containing dopants in the upper inner sidewall is higher than that in the bottom inner sidewall of the trench, the thickness of the silicon oxide layer formed by the thermal oxidation process is larger at the bottom portion than at the upper portion of the trench.

公开(公告)号：US20080273390A1

公开(公告)日：2008-11-06

申请号：US11797613

申请日：2007-05-04

申请人： Chung-We Pan ,  Henry Chang ,  Tzeng-Wen Tzeng ,  Ching-Hung Fu ,  Chih-Ping Chung

发明人： Chung-We Pan ,  Henry Chang ,  Tzeng-Wen Tzeng ,  Ching-Hung Fu ,  Chih-Ping Chung

IPC分类号： G11C11/34 ,  H01L21/82

CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114

摘要： A novel NAND flash memory cell array and the method of fabricating the same are disclosed in this invention. The NAND flash memory cell array comprises a substrate with an active area; a plurality of cells arranged in a row on the active area; a first barrier layer covering the cells and the active area around each end of the row; a first oxide deposited to fill a gap between the cells; an oxide spacer formed along the sidewall of a cell located at each end of the row; and a poly spacer formed on the oxide spacer acting as a selection gate for driving the row of cells. The aspect ratio of the gap between the cells is about 1.8 to 3.2. Many advantages are provided with such NAND flash memory fabricating by the self-aligned process of the present invention.

摘要翻译： 在本发明中公开了一种新颖的NAND闪存单元阵列及其制造方法。 NAND闪存单元阵列包括具有有源面积的衬底; 在所述有效区域上排列成行的多个单元; 覆盖所述电池的第一阻挡层和所述行的每个端部周围的有源区域; 沉积以填充细胞之间的间隙的第一氧化物; 沿着位于行的每个端部的电池的侧壁形成的氧化物间隔物; 以及形成在氧化物隔离物上的聚间隔物，其作为用于驱动该行电池的选择栅极。 细胞间隙的长宽比为1.8〜3.2。 通过本发明的自对准方法制造这种NAND闪速存储器提供了许多优点。

公开(公告)号：US07446027B2

公开(公告)日：2008-11-04

申请号：US11763753

申请日：2007-06-15

申请人： Chiang Yuh Ren

发明人： Chiang Yuh Ren

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L21/28114 ,  H01L21/76897

摘要： A method for forming a gate structure with a pulled-back conductive layer and the use of the method are provided. The method conducts a local, not global, pull-back process on the conductive layer of the gate structure at the position intended for contact window formation, wherein the pull-back process is conducted after rapid thermal oxidation to prevent CBCB short, CB open and/or CBGC short.

摘要翻译： 提供一种用于形成具有拉回导电层的栅极结构的方法和该方法的使用。 该方法在用于接触窗口形成的位置处在栅极结构的导电层上进行局部的，而不是全局的拉回过程，其中拉伸过程在快速热氧化之后进行以防止CBCB短，CB开放和 /或CBGC短。