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    System and method for synchronous machine health monitoring
    121.
    发明授权
    System and method for synchronous machine health monitoring 有权
    同步机健康监测系统及方法

    公开(公告)号：US08803461B2

    公开(公告)日：2014-08-12

    申请号：US12976309

    申请日：2010-12-22

    Applicant: Arvind Kumar Tiwari ,  Arijit Banerjee ,  Hao Huang ,  Xiaochuan Jia ,  Srilatha Boyanapally ,  Rupam Mukherjee

    Inventor： Arvind Kumar Tiwari ,  Arijit Banerjee ,  Hao Huang ,  Xiaochuan Jia ,  Srilatha Boyanapally ,  Rupam Mukherjee

    IPC: H02P3/00

    CPC classification number: H02P23/14 ,  G01R31/343 ,  G01R31/346 ,  H02P25/024 ,  H02P29/0241

    Abstract: A method, system and computer program product for monitoring health of a synchronous machine is provided. The method includes receiving a plurality of phase voltage values and a plurality of phase current values. The method then computes a negative sequence voltage (Vn) based on the plurality of phase voltage values. The method also computes one or more operating parameters based on at least one of the plurality of phase voltage values and the plurality of phase current values. The method retrieves from a data store, one or more known Vn based on the one or more operating parameters. The method then computes a machine health indicator based on the computed Vn and the one or more known Vn, and raises an alarm based on the machine health indicator.

    Abstract translation: 提供了一种用于监测同步机健康状况的方法，系统和计算机程序产品。 该方法包括接收多个相电压值和多个相电流值。 该方法然后基于多个相电压值计算负序电压（Vn）。 该方法还基于多个相电压值和多个相电流值中的至少一个来计算一个或多个操作参数。 该方法基于一个或多个操作参数从数据存储器检索一个或多个已知的Vn。 然后，该方法基于计算的Vn和一个或多个已知的Vn来计算机器健康指示器，并且基于机器健康指示器引发警报。

    Offloading Touch Processing To A Graphics Processor
    122.
    发明申请
    Offloading Touch Processing To A Graphics Processor 有权
    将触摸处理卸载到图形处理器

    公开(公告)号：US20140176573A1

    公开(公告)日：2014-06-26

    申请号：US13785098

    申请日：2013-03-05

    Applicant: Balaji Vembu ,  David I. Poisner ,  Arvind Kumar ,  Chaitanya R. Gandra

    Inventor： Balaji Vembu ,  David I. Poisner ,  Arvind Kumar ,  Chaitanya R. Gandra

    IPC: G06T1/20

    CPC classification number: G06T1/20

    Abstract: In an embodiment, a processor includes a graphics domain including a graphics engines each having at least one execution unit. The graphics domain is to schedule a touch application offloaded from a core domain to at least one of the plurality of graphics engines. The touch application is to execute responsive to an update to a doorbell location in a system memory coupled to the processor, where the doorbell location is written responsive to a user input to the touch input device. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括图形域，包括每个具有至少一个执行单元的图形引擎。 图形域是将从核心域卸载的触摸应用程序调度到多个图形引擎中的至少一个。 所述触摸应用是响应于对耦合到所述处理器的系统存储器中的门铃位置的更新执行的，其中响应于对所述触摸输入设备的用户输入来写入所述门铃位置。 描述和要求保护其他实施例。

    Bulk substrate FET integrated on CMOS SOI
    123.
    发明授权
    Bulk substrate FET integrated on CMOS SOI 有权
    集成在CMOS SOI上的散装衬底FET

    公开(公告)号：US08558313B2

    公开(公告)日：2013-10-15

    申请号：US13425681

    申请日：2012-03-21

    Applicant: Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    Inventor： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    IPC: H01L27/088

    CPC classification number: H01L27/1207 ,  H01L21/84

    Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

    Abstract translation: 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

    Techniques for Enabling Multiple Vt Devices Using High-K Metal Gate Stacks
    129.
    发明申请
    Techniques for Enabling Multiple Vt Devices Using High-K Metal Gate Stacks 有权
    使用高K金属栅极堆栈启用多个Vt器件的技术

    公开(公告)号：US20120181610A1

    公开(公告)日：2012-07-19

    申请号：US13433815

    申请日：2012-03-29

    Applicant: Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

    Inventor： Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

    IPC: H01L27/092

    CPC classification number: H01L27/1104 ,  H01L27/11 ,  H01L27/1108

    Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

    Abstract translation: 提供了用于组合彼此具有不同阈值电压要求的晶体管的技术。 在一个方面，一种半导体器件包括具有第一和第二nFET区的衬底以及第一和第二pFET区; 在第一nFET区域上的衬底上的逻辑nFET; 在第一pFET区上的衬底上的逻辑pFET; 位于第二nFET区上的衬底上的SRAM nFET; 以及在第二pFET区上的衬底上的SRAM pFET，每个包括在高K层上具有金属层的栅极堆叠。 逻辑nFET栅极堆叠还包括将金属层与高K层分隔开的覆盖层，其中封盖层还被配置为相对于逻辑pFET中的一个或多个的阈值电压移动逻辑nFET的阈值电压 ，SRAM nFET和SRAM pFET。

    Method and apparatus for cost and power efficient, scalable operating system independent services
    130.
    发明授权
    Method and apparatus for cost and power efficient, scalable operating system independent services 有权
    用于成本和功率高效，可扩展的操作系统独立服务的方法和设备

    公开(公告)号：US08171321B2

    公开(公告)日：2012-05-01

    申请号：US11964439

    申请日：2007-12-26

    Applicant: Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

    Inventor： Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

    IPC: G06F1/00

    CPC classification number: G06F1/3287 ,  G06F1/3209 ,  Y02D10/171

    Abstract: A low cost, low power consumption scalable architecture is provided to allow a computer system to be managed remotely during all system power states. In a lowest power state, power is only applied to minimum logic necessary to examine a network packet. Power is applied for a short period of time to an execution subsystem and one of a plurality of cores selected to handle processing of received service requests. After processing the received service requests, the computer system returns to the lowest power state.

    Abstract translation: 提供了低成本，低功耗的可扩展架构，以允许在所有系统电源状态期间远程管理计算机系统。 在最低功率状态下，功率仅适用于检查网络分组所需的最小逻辑。 将电力短时间施加到执行子系统，并且被选择用于处理所接收的服务请求的处理的多个核心中的一个。 在处理接收到的服务请求之后，计算机系统返回到最低功率状态。

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