公开(公告)号：US20110228624A1

公开(公告)日：2011-09-22

申请号：US13019858

申请日：2011-02-02

Applicant: Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

Inventor： Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

IPC: G11C8/08

CPC classification number: G11C8/14 ,  G11C8/08

Abstract: Provided is a semiconductor memory device including a sub-word-line driving circuit capable of reducing an amount of leakage current due to coupling. The semiconductor memory device includes a word-line enable signal generating circuit and a sub-word-line driving circuit. The sub-word-line driving circuit provides a pull-down current path between a selected word line and ground for a pulse type period of time in a precharge mode following an active mode for the selected word line, generates a word line driving signal on the basis of a main word line driving signal, a first sub-word-line control signal, and a second sub-word-line control signal, and provides the word line driving signal to a memory cell array. The semiconductor memory device may reduce an amount of leakage current flowing to a ground through the sub-word-line driving circuit.

Abstract translation: 提供了一种半导体存储器件，其包括能够减少由耦合引起的漏电流量的子字线驱动电路。 半导体存储器件包括字线使能信号产生电路和子字线驱动电路。 子字线驱动电路在所选字线的有效模式之后的预充电模式中的脉冲类型时段期间，在所选字线和地之间提供下拉电流路径，生成字线驱动信号 主字线驱动信号的基础，第一子字线控制信号和第二子字线控制信号，并将字线驱动信号提供给存储单元阵列。 半导体存储器件可以减少通过子字线驱动电路流向地的漏电流量。

公开(公告)号：US20110116335A1

公开(公告)日：2011-05-19

申请号：US12821515

申请日：2010-06-23

Applicant: Dong Hyuk LEE ,  Jung-Bae Lee ,  Doo-Gon Kim ,  Cheol Kim

Inventor： Dong Hyuk LEE ,  Jung-Bae Lee ,  Doo-Gon Kim ,  Cheol Kim

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C29/50 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C29/24 ,  G11C29/50016 ,  G11C2211/4061

Abstract: A semiconductor memory device includes a cell array unit having a plurality of banks each having a plurality of blocks, and a refresh controller configured to set at least one of the blocks as a test block, perform a refresh operation on the blocks except for the test block in a self-refresh operation period, determine a refresh period of the test block, and then set another one of the blocks as the test block.

Abstract translation: 半导体存储器件包括具有多个块的单元阵列单元，每个单元具有多个块，以及刷新控制器，被配置为将至少一个块设置为测试块，对除了测试之外的块执行刷新操作 在自刷新操作期间块，确定测试块的刷新周期，然后将另一个块设置为测试块。

公开(公告)号：US07930492B2

公开(公告)日：2011-04-19

申请号：US12006766

申请日：2008-01-04

Applicant: Hoe-Ju Chung ,  Jung-Bae Lee ,  Joo-Sun Choi

Inventor： Hoe-Ju Chung ,  Jung-Bae Lee ,  Joo-Sun Choi

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G11C7/1075

Abstract: A memory system selectively sets signaling modes based on stack position information. The memory system includes a memory module having at least one semiconductor memory device and a memory controller configured to set a signaling mode based on stack position information of each of the semiconductor memory devices. A signaling between the memory controller and each of the semiconductor memory devices is performed in a differential signaling mode, and a signaling among the semiconductor memory devices is performed in a single-ended signaling mode. Accordingly, the memory system has reduced power consumption.

Abstract translation: 存储器系统基于堆栈位置信息选择性地设置信令模式。 存储器系统包括具有至少一个半导体存储器件和存储器控制器的存储器模块，该存储器控制器被配置为基于每个半导体存储器件的堆叠位置信息设置信号模式。 在差分信令模式中执行存储器控制器和每个半导体存储器件之间的信令，并且以单端信令模式执行半导体存储器件之间的信令。 因此，存储系统具有降低的功耗。

公开(公告)号：US20100322021A1

公开(公告)日：2010-12-23

申请号：US12788029

申请日：2010-05-26

Applicant: Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

Inventor： Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

IPC: G11C7/00 ,  G11C8/18

CPC classification number: G11C7/22 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/222 ,  G11C2207/2272

Abstract: A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal.

Abstract translation: 公开了一种半导体存储器件。 半导体器件包括存储单元阵列，时钟信号发生器，被配置为从存储器件的外部接收外部时钟信号并输出​​内部时钟信号;以及数据输出单元，被配置为从存储器单元接收内部数据信号 阵列并响应于内部时钟信号输出读取数据信号。 半导体存储器件还包括读取数据选通单元，其被配置为基于内部时钟信号的周期时间，输出具有n倍（n是等于或大于2的整数）的周期时间的读取数据选通信号 内部时钟信号。

公开(公告)号：US07716401B2

公开(公告)日：2010-05-11

申请号：US11024860

申请日：2004-12-30

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: G06F13/00 ,  H03K17/16 ,  H03K19/003 ,  G11C7/06 ,  G11C5/14

CPC classification number: G11C5/00 ,  G11C5/06 ,  G11C7/1048 ,  G11C11/409 ,  H05K1/0246

Abstract: A memory module and a related memory system are disclosed. The memory module comprises a semiconductor memory having a data output buffer, a data input buffer, a command/address input buffer and a first termination resistor unit connected to a data bus. The memory module further comprises a second termination resistor unit connected to an internal command/address bus. First and second termination resistor units are preferably of different resistive value and/or type.

Abstract translation: 公开了一种存储器模块和相关存储器系统。 存储器模块包括具有数据输出缓冲器，数据输入缓冲器，连接到数据总线的命令/地址输入缓冲器和第一终端电阻器单元的半导体存储器。 存储器模块还包括连接到内部命令/地址总线的第二终端电阻器单元。 第一和第二终端电阻器单元优选地具有不同的电阻值和/或类型。

公开(公告)号：US20090125687A1

公开(公告)日：2009-05-14

申请号：US12266716

申请日：2008-11-07

Applicant: Moon-sook PARK ,  Hoe-ju CHUNG ,  Jung-bae LEE

Inventor： Moon-sook PARK ,  Hoe-ju CHUNG ,  Jung-bae LEE

IPC: G06F12/00

CPC classification number: G11C5/147 ,  G11C5/04

Abstract: The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip, each of the plurality of memory chips including an internal voltage generating circuit, the transfer memory chip configured to receive a plurality of command signals from outside the MCP memory device, the transfer memory chip further configured to output a plurality of control signals to the plurality of memory chips based on the plurality of command signals. Embodiments of the invention also relate to a method of controlling an internal voltage of the MCP memory device.

Abstract translation: 本发明一般涉及一种多芯片封装（MCP）存储器件，尤其涉及但不限于具有减小尺寸的MCP存储器件。 在一个实施例中，MCP存储器件包括：传送存储器芯片; 以及多个存储器芯片，其耦合到所述传送存储器芯片，所述多个存储器芯片中的每一个包括内部电压产生电路，所述传送存储器芯片被配置为从所述MCP存储器设备的外部接收多个命令信号，所述传送存储器芯片 还被配置为基于所述多个命令信号将多个控制信号输出到所述多个存储器芯片。 本发明的实施例还涉及一种控制MCP存储器件的内部电压的方法。

公开(公告)号：US20090091962A1

公开(公告)日：2009-04-09

申请号：US12238720

申请日：2008-09-26

Applicant: Hoe-ju CHUNG ,  Jung-bae LEE ,  Uk-song KANG

Inventor： Hoe-ju CHUNG ,  Jung-bae LEE ,  Uk-song KANG

IPC: G11C5/02 ,  H01L21/00

CPC classification number: G11C5/025 ,  G11C5/02 ,  G11C5/04 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each bank of each memory chip in the stacked plurality of memory chips is commonly addressed to provide read data during a read operation and receive write data during a write operation, and vertically aligned within the stacked plurality of memory chips.

Abstract translation: 多芯片存储器件包括传送输入/输出信号的传输存储器芯片，每个包括具有指定存储体的存储器阵列的堆叠多个存储器芯片，以及通过存储芯片堆栈从传输存储器芯片向上延伸的信号路径 通信输入/输出信号，其中堆叠的多个存储器芯片中的每个存储器芯片的每个存储体通常被寻址以在读取操作期间提供读取数据，并且在写入操作期间接收写入数据，并且在堆叠的多个存储器内垂直对准 筹码

公开(公告)号：US20090039492A1

公开(公告)日：2009-02-12

申请号：US12123583

申请日：2008-05-20

Applicant: Uk-song KANG ,  Jung-bae LEE ,  Hoe-ju CHUNG

Inventor： Uk-song KANG ,  Jung-bae LEE ,  Hoe-ju CHUNG

IPC: H01L23/02

CPC classification number: G11C5/025 ,  G11C5/02 ,  G11C5/063 ,  H01L25/0657 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15331 ,  H01L2224/05599

Abstract: A semiconductor memory device includes a stacked plurality of interposer chips, each interposer chip seating a smaller corresponding memory chip, wherein a lowermost interposer chip in the stacked plurality of interposer chips is mounted on a buffer chip. Each one of the stacked plurality of interposer chips includes a central portion having bond pads seating the corresponding memory device and a peripheral portion having a plurality of through silicon vias (TSVs). The respective pluralities of TSVs for adjacent interposer chips in the stacked plurality of interposer chips are connected via vertical connection elements to form multiple internal signal paths communicating write data from and read data to the buffer chip from respective memory chips.

Abstract translation: 半导体存储器件包括堆叠的多个插入器芯片，每个插入器芯片放置较小的对应的存储器芯片，其中堆叠的多个插入器芯片中的最下层插入器芯片安装在缓冲芯片上。 堆叠的多个插入器芯片中的每一个包括具有连接衬垫对应的存储器件的中心部分和具有多个穿通硅通孔（TSV）的外围部分。 堆叠的多个插入器芯片中的相邻插入器芯片的相应多个TSV通过垂直连接元件连接，以形成从相应存储器芯片向缓冲器芯片传送写入数据和从其读取数据的多个内部信号路径。

公开(公告)号：US20080256414A1

公开(公告)日：2008-10-16

申请号：US12044183

申请日：2008-03-07

Applicant: Hoe-Ju CHUNG ,  Jung-Bae LEE

Inventor： Hoe-Ju CHUNG ,  Jung-Bae LEE

IPC: G06F11/10 ,  G11C5/06

CPC classification number: G06F11/1008 ,  G11C5/02 ,  G11C5/04 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1045 ,  G11C2029/0411 ,  H04L1/0041 ,  H04L1/0057

Abstract: A system, device and related method are used to communicate data via a plurality of data lanes including a selected data lane. In a first mode of operation, payload data and related supplemental data are communicated via the plurality of data lanes including the selected data lane. In a second mode of operation, only payload data is communicated via the plurality of data lanes, except the selected data lane.

Abstract translation: 系统，设备和相关方法用于经由包括所选择的数据通道的多个数据通道来传送数据。 在第一操作模式中，经由包括所选择的数据通道的多个数据通道来传送有效载荷数据和相关的补充数据。 在第二种操作模式中，只有有效载荷数据经由多个数据通道被传送，除了所选择的数据通道。

公开(公告)号：US20080151651A1

公开(公告)日：2008-06-26

申请号：US11836283

申请日：2007-08-09

Applicant: Sang-yun Kim ,  Jung-bae Lee ,  Young-don Choi

Inventor： Sang-yun Kim ,  Jung-bae Lee ,  Young-don Choi

IPC: G11C7/00

CPC classification number: G11C7/1006

Abstract: A semiconductor memory device utilizing a data coding method in an initial operation. The semiconductor memory device includes a plurality of counters communicating with a data coding unit. The counters count the number of data bits and flag information data bits in a first logic state in a first data group which includes at least one data bit and second through nth groups each including at least one data bit and flag information. The data coding unit selectively applies a first operation mode and a second operation mode to each of the first through nth data groups and codes the data of each of the first through nth data groups. The first operation mode codes the data of each of the first through nth data groups such that the counted number of data bits in the first logic state in each of the first through nth groups is minimized. The second operation mode codes the data of each of the first through nth groups such that the difference between the number of data bits and flag information data bits in the first logic state and the number of data bits and flag information data bits in a second logic state in the first through nth data groups is minimized. In this manner, the semiconductor memory device and the associated data coding method prevents the initial logic state of data from being changed due to a voltage drop in the initial operation of the device.

Abstract translation: 一种在初始操作中利用数据编码方法的半导体存储器件。 半导体存储器件包括与数据编码单元通信的多个计数器。 计数器在包括至少一个数据位和第二至第n组的第一数据组中对第一逻辑状态中的数据位和标志信息数据位的数目进行计数，每个包括至少一个数据位和标志信息。 数据编码单元选择性地对第一至第n数据组中的每一个应用第一操作模式和第二操作模式，并对第一至第n数据组中的每一个的数据进行编码。 第一操作模式对第一至第n数据组中的每一个的数据进行编码，使得第一至第n组中的每一个中的第一逻辑状态中的数据位的计数数量最小化。 第二操作模式对第一至第n组中的每一个的数据进行编码，使得第一逻辑状态中的数据位数和标志信息数据位之间的差异以及第二逻辑中的数据位和标志信息数据位的数量 在第一至第n个数据组中的状态被最小化。 以这种方式，半导体存储器件和相关联的数据编码方法防止数据的初始逻辑状态由于器件的初始操作中的电压降而被改变。