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    CONTROLLING DEPTH AND LATENCY OF EXIT OF A VIRTUAL PROCESSOR'S IDLE STATE IN A POWER MANAGEMENT ENVIRONMENT
    121.
    发明申请
    CONTROLLING DEPTH AND LATENCY OF EXIT OF A VIRTUAL PROCESSOR'S IDLE STATE IN A POWER MANAGEMENT ENVIRONMENT 审中-公开
    控制电源管理环境中虚拟处理器空闲状态的深度和失效

    公开(公告)号：US20120198452A1

    公开(公告)日：2012-08-02

    申请号：US13445051

    申请日：2012-04-12

    申请人： RICHARD L. ARNDT ,  NARESH NAYAR ,  CHRISTOPHER FRANCOIS ,  KARTHICK RAJAMANI ,  FREEMAN L. RAWSON, III ,  RANDAL C. SWANBERG

    发明人： RICHARD L. ARNDT ,  NARESH NAYAR ,  CHRISTOPHER FRANCOIS ,  KARTHICK RAJAMANI ,  FREEMAN L. RAWSON, III ,  RANDAL C. SWANBERG

    IPC分类号： G06F9/455

    CPC分类号： G06F9/45533 ,  G06F9/45541 ,  G06F2009/45575

    摘要： A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor.

    摘要翻译： 在逻辑分区的数据处理系统中提供一种机制，用于控制虚拟处理器的空闲状态的退出的深度和等待时间。 一个虚拟化层产生一个雪松延迟设置信息（CLSI）数据。 响应于引导逻辑分区，虚拟化层将CLSI数据传送到逻辑分区的操作系统（OS）。 OS根据CLSI数据确定在OS控制下的虚拟处理器的特定空闲状态。 响应于调用虚拟化层的OS，OS将虚拟处理器的特定空闲状态传送到虚拟化层，以将特定的空闲状态和唤醒特性分配给虚拟处理器。

    Transparently Increasing Power Savings in a Power Management Environment
    124.
    发明申请
    Transparently Increasing Power Savings in a Power Management Environment 失效
    在电源管理环境中透明地增加节能

    公开(公告)号：US20110320840A1

    公开(公告)日：2011-12-29

    申请号：US12821789

    申请日：2010-06-23

    申请人： Naresh Nayar ,  Karthick Rajamani ,  Freeman L. Rawson, III

    发明人： Naresh Nayar ,  Karthick Rajamani ,  Freeman L. Rawson, III

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3203 ,  G06F9/5077 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/36

    摘要： A mechanism is provided for transparently consolidating resources of logical partitions. Responsive to the existence of the non-folded resource on an originating resource chip, the virtualization mechanism determines whether there is a destination resource chip to either exchange operations of the non-folded resource with a folded resource on the destination chip or migrate operations of the non-folded resource to a non-folded resource on the destination chip. Responsive to the existence of the folded resource on the destination resource chip, the virtualization mechanism transparently exchanges the operations of the non-folded resource from the originating resource chip to the folded resource on the destination resource chip, where the folded resource remains folded on the originating resource chip after the exchange. Responsive to the absence of another non-folded resource on the originating resource chip, the vitalization mechanism places the originating resource chip into a deeper power saving mode.

    摘要翻译： 提供了一种用于透明地整合逻辑分区资源的机制。 响应于原始资源芯片上的非折叠资源的存在，虚拟化机制确定是否存在目的地资源芯片，以在目的地芯片上用折叠资源来交换非折叠资源的操作，或者迁移操作 非折叠资源到目标芯片上的非折叠资源。 响应于目标资源芯片上折叠资源的存在，虚拟化机制透明地将未折叠资源的操作从始发资源芯片交换到目的地资源芯片上的折叠资源，其中折叠资源保持折叠在 交换后的源资源芯片。 响应于起始资源芯片上不存在另一非折叠资源，激活机制将始发资源芯片置于更深的省电模式。

    EFFICIENT SUPPORT OF MULTIPLE PAGE SIZE SEGMENTS
    125.
    发明申请
    EFFICIENT SUPPORT OF MULTIPLE PAGE SIZE SEGMENTS 有权
    有效支持多页尺寸段

    公开(公告)号：US20110276778A1

    公开(公告)日：2011-11-10

    申请号：US12775652

    申请日：2010-05-07

    申请人： Miles R. Dooley ,  Sundeep Chadha ,  Naresh Nayar ,  Randal C. Swanberg

    发明人： Miles R. Dooley ,  Sundeep Chadha ,  Naresh Nayar ,  Randal C. Swanberg

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F2212/652

    摘要： An apparatus, system, and method are disclosed for improved support of MPS segments in a microprocessor. The virtual address is used to generate possible TLB index values for each of the supported page sizes of the MPS segment associated with the virtual address. The possible TLB index values may be a hash generated using the virtual address and one of the supported page sizes. The TLB is searched for actual TLB index values that match the possible TLB index values calculated using the different supported page sizes. TLB entries associated with those actual TLB index values are checked to determine whether any TLB entry is associated with the virtual address. If no match is found, the real address is retrieved from the PT. The actual page size in the PT is used to generate an actual TLB index value for the virtual address and the TLB entry is inserted into the TLB.

    摘要翻译： 公开了一种用于改进对微处理器中的MPS段的支持的装置，系统和方法。 虚拟地址用于为与虚拟地址相关联的MPS段的每个支持的页面大小生成可能的TLB索引值。 可能的TLB索引值可以是使用虚拟地址和支持的页面大小之一生成的哈希值。 搜索与使用不同的支持的页面大小计算的可能的TLB索引值相匹配的实际TLB索引值的TLB。 检查与这些实际TLB索引值相关联的TLB条目以确定是否有任何TLB条目与虚拟地址相关联。 如果没有找到匹配，则从PT检索真实地址。 PT中的实际页面大小用于生成虚拟地址的实际TLB索引值，并将TLB条目插入到TLB中。

    Controlling Power Management Policies on a Per Partition Basis in a Virtualized Environment
    127.
    发明申请
    Controlling Power Management Policies on a Per Partition Basis in a Virtualized Environment 审中-公开
    控制虚拟化环境中每个分区的电源管理策略

    公开(公告)号：US20110145555A1

    公开(公告)日：2011-06-16

    申请号：US12637808

    申请日：2009-12-15

    申请人： Naresh Nayar ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Todd J. Rosedahl ,  Malculm S. Ware

    发明人： Naresh Nayar ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Todd J. Rosedahl ,  Malculm S. Ware

    IPC分类号： G06F1/26 ,  G06F12/00 ,  G06F12/02 ,  G06F15/177

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  Y02D10/126

    摘要： A mechanism is provided for controlling power management policies on a per logical partition basis. A power management mechanism in a data processing system receives a notification that the logical partition has been generated, a set of processing units associated with the logical partition, and a current power management policy to be implemented for the logical partition. The power management mechanism adds the logical partition and the set of processing units to a list of logical partitions. The power management mechanism initializes the set of processing units based on settings for the set of processing units in the current power management policy. The power management mechanism notifies a virtualization mechanism that the set of processing units are running at a specified performance level in order for the logical partition to start executing tasks on the set of processing units.

    摘要翻译： 提供了一种用于在每个逻辑分区的基础上控制功率管理策略的机制。 数据处理系统中的电源管理机制接收到已经生成逻辑分区的通知，与逻辑分区相关联的一组处理单元以及要为逻辑分区实现的当前功率管理策略。 电源管理机制将逻辑分区和一组处理单元添加到逻辑分区列表中。 电源管理机制根据当前电源管理策略中的一组处理单元的设置初始化一组处理单元。 电源管理机制通知虚拟化机构，该组处理单元以指定的性能级别运行，以使逻辑分区开始在该组处理单元上执行任务。

    Power-aware line intervention for a multiprocessor snoop coherency protocol
    128.
    发明授权
    Power-aware line intervention for a multiprocessor snoop coherency protocol 有权
    多处理器侦听一致性协议的功率感知线路干预

    公开(公告)号：US07870337B2

    公开(公告)日：2011-01-11

    申请号：US11946249

    申请日：2007-11-28

    申请人： Robert H. Bell, Jr. ,  Louis B. Capps, Jr. ,  Thomas E. Cook ,  Michael J. Shapiro ,  Naresh Nayar

    发明人： Robert H. Bell, Jr. ,  Louis B. Capps, Jr. ,  Thomas E. Cook ,  Michael J. Shapiro ,  Naresh Nayar

    IPC分类号： G06F13/00 ,  G06F13/28 ,  G01R21/00 ,  G01R21/06 ,  G01R19/00

    CPC分类号： G06F12/0831 ,  G06F2212/1028 ,  Y02D10/13

    摘要： A snoop coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.

    摘要翻译： 提供窥探一致性方法，系统和程序，用于基于每个存储器源处的感测温度或功率耗散值，在多处理器系统中从多个候选存储器源插入所请求的高速缓存行。 通过在共享所请求的高速缓存行的每个候选存储器源（例如，在内核，高速缓冲存储器，存储器控制器等）中提供温度或功率耗散传感器，可以使用控制逻辑来确定哪个存储器源应该来源于高速缓存 通过使用功率传感器信号仅以可接受的功率消耗信号通知存储器源，以向请求器提供高速缓存线。

    Partition Transparent Memory Error Handling in a Logically Partitioned Computer System With Mirrored Memory
    129.
    发明申请
    Partition Transparent Memory Error Handling in a Logically Partitioned Computer System With Mirrored Memory 有权
    在具有镜像内存的逻辑分区计算机系统中分区透明内存错误处理

    公开(公告)号：US20090282300A1

    公开(公告)日：2009-11-12

    申请号：US12115625

    申请日：2008-05-06

    申请人： Peter Joseph Heyrman ,  Naresh Nayar ,  Gary Ross Ricard

    发明人： Peter Joseph Heyrman ,  Naresh Nayar ,  Gary Ross Ricard

    IPC分类号： G06F11/07

    CPC分类号： G06F11/2082 ,  G06F11/2094

    摘要： A method and apparatus for transparently handling recurring correctable errors and uncorrectable errors in a mirrored memory system prevents costly system shutdowns for correctable memory errors or system failures from uncorrectable memory errors. When a high number of correctable errors are detected for a given memory location, a memory relocation mechanism in the hypervisor moves the data associated with the memory location to an alternate physical memory location transparently to the partition such that the partition has no knowledge that the physical memory actualizing the memory location has been changed. When a correctable error occurs, the memory relocation mechanism uses data from a partner mirrored memory block as a data source for the memory block with the uncorrectable error and then relocates the data to a newly allocated memory block to replace the memory block with the uncorrectable error.

    摘要翻译： 用于透明地处理镜像存储器系统中的可重复校正错误和不可校正错误的方法和装置防止由于不可校正的存储器错误而导致的可校正存储器错误或系统故障的昂贵的系统关闭。 当对于给定的存储器位置检测到大量的可校正错误时，管理程序中的存储器重定位机制将与存储器位置相关联的数据透明地移动到备用物理存储器位置到分区，使得分区不知道物理 内存实现内存位置已更改。 当发生可纠正错误时，内存重定位机制使用来自伙伴镜像内存块的数据作为具有不可校正错误的存储器块的数据源，然后将数据重新定位到新分配的存储器块以用不可校正的错误来替换存储器块 。

    Executing An Overall Quantity Of Data Processing Within An Overall Processing Period
    130.
    发明申请
    Executing An Overall Quantity Of Data Processing Within An Overall Processing Period 有权
    在整个处理期间执行总体数据处理量

    公开(公告)号：US20090112518A1

    公开(公告)日：2009-04-30

    申请号：US12349877

    申请日：2009-01-07

    申请人： Troy David Armstrong ,  Naresh Nayar ,  Gary R. Ricard

    发明人： Troy David Armstrong ,  Naresh Nayar ,  Gary R. Ricard

    IPC分类号： G06F11/30

    CPC分类号： G06F9/485 ,  G06F9/4881

    摘要： Exemplary methods, systems, and products are described for executing an overall quantity of data processing within an overall processing period that include executing repeatedly through a series of iterations a portion of the overall quantity of data processing that can be completed in a set processing period, wherein each iteration includes the set processing period and a variable delay period and calculating the variable delay period for an iteration in dependence upon the set processing period, a portion of the overall quantity of data processing performed during the set processing period of the iteration, the overall quantity of data processing, and the overall processing period.

    摘要翻译： 描述了用于在整个处理周期内执行总体数据处理的示例性方法，系统和产品，其包括通过一系列迭代重复地执行可以在设定的处理周期内完成的整个数据处理量的一部分， 其中每次迭代包括设置处理周期和可变延迟周期，并且根据设定的处理周期计算迭代的可变延迟周期，在迭代的设置处理周期期间执行的总数量处理的一部分， 总体数据处理量和总体处理时间。