公开(公告)号：US20190229726A1

公开(公告)日：2019-07-25

申请号：US16249065

申请日：2019-01-16

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Sergio Lecce ,  Gilles Troussel

IPC: H03K17/687 ,  G05F3/26 ,  G06F13/20 ,  H04L12/40

Abstract: A driver circuit includes a supply node, a control node configured to receive a control signal, and an output node. An output transistor is coupled to the output node to provide the CAN bus drive signal via the current path through the output transistor. A current mirror is in a current line from the supply node to the output node through the output transistor. The current line includes an intermediate portion between the current mirror and the output transistor. The current mirror is configured to be switched, as a function of the control signal between a first, dominant mode, with the CAN bus drive signal applied to the output node via the output transistor, and a second, recessive mode, with the output transistor providing a high output impedance at the output node.

公开(公告)号：US20190214274A1

公开(公告)日：2019-07-11

申请号：US16240220

申请日：2019-01-04

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David AUCHERE

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H05K1/11 ,  H01L23/31

CPC classification number: H01L21/486 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49827 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/73103 ,  H05K1/113 ,  H05K2201/09563

Abstract: An insulating spacer provides electrical connection between first contacts of a package for an electronic chip and second contacts of a connector board. The insulating spacer includes conductive vias having rectilinear axes parallel to one another which extend between the first and second contacts. The package for an electronic chip is mounted to one side of the insulating spacer and the connector board is mounted to an opposite side of the insulating spacer.

公开(公告)号：US20190205260A1

公开(公告)日：2019-07-04

申请号：US16296706

申请日：2019-03-08

Applicant: STMicroelectronics (Grenoble 2) SAS ,  Technological Educational Institute of Crete

Inventor： Antonio-Marcello Coppola ,  Georgios Kornaros ,  Miltos Grammatikakis

IPC: G06F12/1009 ,  G06F9/445 ,  G06F15/167

CPC classification number: G06F12/1009 ,  G06F9/44505 ,  G06F15/167 ,  G06F2212/657

Abstract: An apparatus includes a first processor to execute a user-level application to operate in a virtual address, and a co-processor to execute a computing kernel associated with user-level application elements to be performed on the co-processor. The computing kernel is to operate in the virtual address. A memory includes physical addresses, and a partition used to map the virtual address associated with the first processor and to map the virtual address associated with the co-processor. A packet processor manages communications between the first processor and the co-processor. The packet processor receives packets from the first processor, with the packets including memory addresses identifying code and data of the computing kernel. The packet processor stores the packets in a queue associated with the user-level application, and outputs the packets to the co-processor, such that the co-processor is enabled to execute the computing kernel.

公开(公告)号：US10306248B2

公开(公告)日：2019-05-28

申请号：US14929129

申请日：2015-10-30

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Jacques Talayssat ,  Sébastien Cleyet-Merle ,  Vitor Schwambach Costa

IPC: G06K9/46 ,  H04N19/426 ,  G06K9/26 ,  G06K9/62 ,  G06K9/00

Abstract: A method and device for real-time generation of a multiresolution representation of a digital image for real-time generation are disclosed. A sequence of main representations of the digital image is stored at successive different main resolutions in a main memory. A part of a current main representation is loaded from the main memory into a local memory via a bus. A current main representation is processed by determining a corresponding part of an intermediate representation of the image having an intermediate resolution lying between the resolution of the current main representation and the resolution of the subsequent main representation. The loading and processing steps are repeated for other parts of the current main representation until all parts of the current main representation have been successively loaded and processed.

公开(公告)号：US10292259B2

公开(公告)日：2019-05-14

申请号：US15142213

申请日：2016-04-29

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Laurent Marechal ,  Richard Rembert ,  Jerome Lopez

IPC: H02K1/02 ,  H05K1/02

Abstract: An electronic device disclosed herein includes a first conductor layer, a first nonconducting layer, and a second conductor layer in a stacked arrangement. A signal carrying conductive via is formed in the first nonconducting layer and extends between the first conductor layer and the second conductor layer. A shielding conductive via is formed in the first nonconducting layer, is not electrically coupled to the signal carrying conductive via, and substantially completely surrounds the signal carrying conductive via in spaced apart relation thereto.

公开(公告)号：US10261912B2

公开(公告)日：2019-04-16

申请号：US15402515

申请日：2017-01-10

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  Technological Educational Institute of Crete

Inventor： Antonio-Marcello Coppola ,  Georgios Kornaros ,  Miltos Grammatikakis

IPC: G06F12/10 ,  G06F9/54 ,  G06F15/167 ,  G06F12/1009 ,  G06F9/445

Abstract: An apparatus includes a first processor to execute a user-level application to operate in a virtual address, and a co-processor to execute a computing kernel associated with user-level application elements to be performed on the co-processor. The computing kernel is to operate in the virtual address. A memory includes physical addresses, and a partition used to map the virtual address associated with the first processor and to map the virtual address associated with the co-processor. A packet processor manages communications between the first processor and the co-processor. The packet processor receives packets from the first processor, with the packets including memory addresses identifying code and data of the computing kernel. The packet processor stores the packets in a queue associated with the user-level application, and outputs the packets to the co-processor, such that the co-processor is enabled to execute the computing kernel.

公开(公告)号：US20190103368A1

公开(公告)日：2019-04-04

申请号：US16208038

申请日：2018-12-03

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Karine SAXOD ,  Marika SORRIEUL

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L27/146 ,  H01L25/065 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/18 ,  H01L23/48

Abstract: A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring.

公开(公告)号：US10236842B2

公开(公告)日：2019-03-19

申请号：US15393485

申请日：2016-12-29

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Vratislav Michal ,  Michel Ayraud

IPC: H03F3/45 ,  H03F1/02 ,  G01R1/30 ,  G01R31/36

Abstract: A circuit includes an amplifier having a first power terminal configured to be coupled to a supply voltage and a second power terminal configured to be coupled to a reference potential. The circuit further includes a first impedance element coupled between a first input terminal of the amplifier and a first output terminal of the amplifier. The circuit additionally includes a second impedance element coupled between the first input terminal and the reference potential. The amplifier is configured to output a first voltage at a second output terminal of the amplifier in response to the supply voltage being greater than an output voltage at the first output terminal of the amplifier. The amplifier is further configured to output a second voltage at the second output terminal of the amplifier in response to the supply voltage being less than the output voltage at the first output terminal of the amplifier.

公开(公告)号：US10222855B2

公开(公告)日：2019-03-05

申请号：US15444724

申请日：2017-02-28

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jean Camiolo ,  Christophe Lorin

IPC: G06F1/32 ,  G06F13/38 ,  G06F13/42 ,  G06F13/24 ,  G06F1/16 ,  G06F1/3296 ,  G05F1/00 ,  G06F1/26 ,  G06F1/3287 ,  H01R24/28 ,  H01R24/60 ,  H01R107/00

Abstract: A method can be used for managing a power supply voltage on an output power supply pin of a USB Type-C source device coupled to a USB Type-C receiver device via a USB Type-C cable. A first measurement of a first voltage on a channel configuration pin of the cable is performed when the receiver device is not powered and a second measurement of a second voltage on the channel configuration pin is performed when the receiver device is powered. A difference between the first and second voltages is calculated and the power supply voltage is modified as a function of a value of the difference.

公开(公告)号：US10177098B2

公开(公告)日：2019-01-08

申请号：US15410230

申请日：2017-01-19

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Karine Saxod ,  Marika Sorrieul

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L27/146 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/18

Abstract: A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring.