Class D amplifier circuit
    121.
    发明授权

    公开(公告)号:US09628040B2

    公开(公告)日:2017-04-18

    申请号:US14836006

    申请日:2015-08-26

    Abstract: This application relates to Class D amplifier circuits (200). A modulator (201) controls a Class D output stage (202) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block (205), which may comprise an ADC (207), generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input (204) of a signal selector block (203). The input signal may be received at a second input (206) of the signal selector block (203). The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block (205).

    Detection of replay attack
    122.
    发明授权

    公开(公告)号:US12288553B2

    公开(公告)日:2025-04-29

    申请号:US17261786

    申请日:2019-07-31

    Abstract: A method of detecting a replay attack comprises: receiving an audio signal representing speech; identifying speech content present in at least a portion of the audio signal; obtaining information about a frequency spectrum of each portion of the audio signal for which speech content is identified; and, for each portion of the audio signal for which speech content is identified: retrieving information about an expected frequency spectrum of the audio signal; comparing the frequency spectrum of portions of the audio signal for which speech content is identified with the respective expected frequency spectrum; and determining that the audio signal may result from a replay attack if a measure of a difference between the frequency spectrum of the portions of the audio signal for which speech content is identified and the respective expected frequency spectrum exceeds a threshold level.

    Speech recognition
    123.
    发明授权

    公开(公告)号:US12183333B2

    公开(公告)日:2024-12-31

    申请号:US17549528

    申请日:2021-12-13

    Abstract: A speech recognition system comprises: an input, for receiving an input signal from at least one microphone; a first buffer, for storing the input signal; a noise reduction block, for receiving the input signal and generating a noise reduced input signal; a speech recognition engine, for receiving either the input signal output from the first buffer or the noise reduced input signal from the noise reduction block; and a selection circuit for directing either the input signal output from the first buffer or the noise reduced input signal from the noise reduction block to the speech recognition engine.

    Amplifier circuitry
    125.
    发明授权

    公开(公告)号:US11909362B2

    公开(公告)日:2024-02-20

    申请号:US17835326

    申请日:2022-06-08

    Inventor: John Paul Lesso

    CPC classification number: H03F3/217 H03F2200/129 H03F2200/165

    Abstract: This application relates to amplifier circuitry, in particular class-D amplifiers, operable in open-loop and closed-loop modes. An amplifier (300) has a forward signal path for receiving an input signal (SIN) and outputting an output signal (SOUT) and a feedback path operable to provide a feedback signal (SFB) from the output. A feedforward path provide a feedforward signal (SFF) from the input and a combiner (105) is operable to determine an error signal (ε) based on a difference between the feedback signal and the feedforward signal. The feedforward comprises a compensation module (201) configured to apply a controlled transfer function to the feedforward signal in the closed-loop mode of operation, such that an overall transfer function for the amplifier is substantially the same in the closed-loop mode of operation and the open-loop mode of operation.

    Computing circuitry
    126.
    发明授权

    公开(公告)号:US11880728B2

    公开(公告)日:2024-01-23

    申请号:US18296297

    申请日:2023-04-05

    Inventor: John Paul Lesso

    CPC classification number: G06G7/48 G06N3/065 H02M1/0845 H03M1/06 H03M1/12

    Abstract: This application relates to computing circuitry, and in particular to analogue computing circuitry suitable for neuromorphic computing. An analogue computation unit for processing data is supplied with a first voltage from a voltage regulator which is operable in a sequence of phases to cyclically regulate the first voltage. A controller is configured to control operation of the voltage regulator and/or the analogue computation unit, such that the analogue computation unit processes data during a plurality of compute periods that avoid times at which the voltage regulator undergoes a phase transition which is one of a predefined set of phase transitions between defined phases in said sequence of phases. This avoids performing computation operations during a phase transition of the voltage regulator that could result in a transient or disturbance in the first voltage, which could adversely affect the computing.

    Analog neural network systems
    129.
    发明授权

    公开(公告)号:US11748608B2

    公开(公告)日:2023-09-05

    申请号:US16844551

    申请日:2020-04-09

    Inventor: John Paul Lesso

    CPC classification number: G06N3/065 G06N3/04 G11C13/00

    Abstract: The present disclosure relates to a neural network system comprising: a data input configured to receive an input data signal and analog neural network circuitry having an input coupled with the data input. The analog neural network circuitry is operative to apply a weight to a signal received at its input to generate a weighted output signal. The neural network system further comprises compensation circuitry configured to apply a compensating term to the input data signal to compensate for error in the analog neural network circuitry.

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