-
公开(公告)号：US07517764B2
公开(公告)日：2009-04-14
申请号：US11427486
申请日：2006-06-29
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.
摘要翻译： finFET结构和finFET结构的制造方法。 该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。 该结构包括在finFET的硅体和衬底之间的体接触。
-
公开(公告)号：US07491994B2
公开(公告)日：2009-02-17
申请号：US11216387
申请日：2005-08-31
IPC分类号： H01L29/94
CPC分类号： G11C11/15 , H01L27/1203 , H01L43/065
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory cell that includes (1) a semiconductor fin enclosure formed on an insulating layer of a substrate; and (2) a ferromagnetic material within the semiconductor fin enclosure. A top surface of the ferromagnetic material is below a top surface of the semiconductor fin enclosure. Numerous other aspects are provided.
摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是存储单元，其包括：（1）形成在基板的绝缘层上的半导体翅片外壳; 和（2）半导体翅片外壳内的铁磁材料。 铁磁材料的顶表面位于半导体翅片外壳的顶表面之下。 提供了许多其他方面。
-
123.发明申请公开(公告)号：US20080283917A1
公开(公告)日：2008-11-20
申请号：US12143213
申请日：2008-06-20
IPC分类号： H01L29/786
CPC分类号： H01L29/785 , H01L29/66795
摘要： Methods of fabricating a semiconductor structure in which a body of monocrystalline silicon is formed on a sidewall of a sacrificial mandrel and semiconductor structures made by the methods. After the body of monocrystalline silicon is formed, the sacrificial material of the mandrel is removed selective to the monocrystalline silicon of the body. The mandrel may be composed of porous silicon and the body may be fabricated using either a semiconductor-on-insulator substrate or a bulk substrate. The body may be used to fabricate a fin body of a fin-type field effect transistor.
摘要翻译： 制造半导体结构的方法，其中在牺牲心轴的侧壁上形成单晶硅体，并通过该方法制造半导体结构。 在形成单晶硅体之后，心轴的牺牲材料被选择性地去除到主体的单晶硅上。 心轴可以由多孔硅组成，并且主体可以使用绝缘体上半导体衬底或块状衬底来制造。 本体可用于制造翅片型场效应晶体管的翅片体。
-
124.发明申请Semiconductor Device Structures and Methods of Fabricating Semiconductor Device Structures for Use in SRAM Devices 审中-公开制造用于SRAM器件的半导体器件结构的半导体器件结构和方法公开(公告)号：US20080251934A1
公开(公告)日：2008-10-16
申请号：US11734931
申请日：2007-04-13
申请人： Jack Allan Mandelman , Haining Yang
发明人： Jack Allan Mandelman , Haining Yang
IPC分类号： H01L29/267 , H01L21/3205
CPC分类号： H01L27/11 , H01L21/76889 , H01L21/76895 , H01L27/1104
摘要： Semiconductor device structures and methods of fabricating such semiconductor device structures for use in static random access memory (SRAM) devices. The semiconductor device structure comprises a dielectric region disposed between first and second semiconductor regions and a gate conductor structure extending between the first and second semiconductor regions. The gate conductor structure has a first sidewall overlying the first semiconductor region. The device structure further comprises an electrically connective bridge extending across the first semiconductor region. The electrically connective bridge has a portion that electrically connects a impurity-doped region in the first semiconductor region with the first sidewall of the gate conductor structure.
摘要翻译： 用于制造用于静态随机存取存储器（SRAM）器件的这种半导体器件结构的半导体器件结构和方法。 半导体器件结构包括设置在第一和第二半导体区域之间的介质区域和在第一和第二半导体区域之间延伸的栅极导体结构。 栅极导体结构具有覆盖第一半导体区域的第一侧壁。 器件结构还包括延伸跨越第一半导体区域的电连接桥。 电连接桥具有将第一半导体区域中的杂质掺杂区域与栅极导体结构的第一侧壁电连接的部分。
-
公开(公告)号：US20080233699A1
公开(公告)日：2008-09-25
申请号：US12133440
申请日：2008-06-05
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.
摘要翻译： finFET结构和finFET结构的制造方法。 该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。 该结构包括在finFET的硅体和衬底之间的体接触。
-
126.发明申请APPARATUS FOR IMPLEMENTING ENHANCED HAND SHAKE PROTOCOL IN MICROELECTRONIC COMMUNICATION SYSTEMS 失效用于在微电子通信系统中实施增强手抖协议的装置公开(公告)号：US20080227425A1
公开(公告)日：2008-09-18
申请号：US12127159
申请日：2008-05-27
IPC分类号： H04B1/16
CPC分类号： H04B1/38
摘要： A method and apparatus are provided for implementing an enhanced hand shake protocol for microelectronic communication systems. A transmitter and a receiver is coupled together by a transmission link. The transmitter receives an idle input. The idle input is activated when the transmitter is not transmitting data and the transmitter applies a first common mode level to the receiving unit. The idle input is deactivated when the transmitter is ready to transmit data and the transmitter raises the common mode level to the receiving unit. Responsive to the receiver detecting the common mode level up-movement, then the receiver receives the transmitted data signals. After the desired data has been sent, the transmitter terminates communications, drops the common mode level with the idle input being activated.
摘要翻译： 提供了一种用于实现用于微电子通信系统的增强的手抖动协议的方法和装置。 发射机和接收机通过传输链路耦合在一起。 发射机接收空闲输入。 当发射机不发送数据并且发射机向接收单元应用第一共模电平时，空闲输入被激活。 当发射机准备好传输数据并且发射机将共模电平提升到接收单元时，空闲输入被去激活。 响应于接收机检测共模水平上移，接收器接收发送的数据信号。 在所需数据被发送之后，发射机终止通信，在空闲输入被激活时降低共模电平。
-
公开(公告)号：US20080203468A1
公开(公告)日：2008-08-28
申请号：US11680221
申请日：2007-02-28
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66818
摘要： Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.
摘要翻译： 本发明的实施例提供了Fin场效应晶体管（FinFET）中的相对均匀的宽度鳍片及其形成方法。 翅片结构可以形成为使翅片结构的侧壁部分的表面垂直于第一结晶方向。 翅片结构端部的锥形区域可以垂直于第二晶体方向。 可以对翅片结构进行晶体依赖蚀刻。 晶体依赖蚀刻可以相对较快地从第二晶体方向垂直于翅片的部分去除材料，从而形成相对均匀的宽度鳍片结构。
-
128.发明授权公开(公告)号：US07335575B2
公开(公告)日：2008-02-26
申请号：US11347332
申请日：2006-02-03
CPC分类号： H01L23/3677 , H01L2924/0002 , H01L2924/10158 , Y10S438/928 , Y10S438/96 , Y10S438/977 , H01L2924/00
摘要： A method of fabricating a semiconductor device includes etching a substrate to form a recess, the substrate being formed on a backside of a semiconductor wafer, forming pores in the substrate in an area of the recess, and forming in the recess a material having a thermal conductivity which is greater than a thermal conductivity of the substrate. In another aspect, a method of fabricating a semiconductor device includes etching a substrate formed on a backside of a semiconductor wafer to form a recess in the substrate, and forming a sputter film in the recess, the sputter film including a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of the substrate, and a second material having a thermal conductivity which is greater than a thermal conductivity of the substrate.
摘要翻译： 一种制造半导体器件的方法包括蚀刻衬底以形成凹部，所述衬底形成在半导体晶片的背面上，在所述凹部的区域中在所述衬底中形成孔，并且在所述凹部中形成具有热 电导率大于衬底的热导率。 另一方面，制造半导体器件的方法包括蚀刻形成在半导体晶片的背面上的衬底，以在衬底中形成凹陷，并且在凹部中形成溅射膜，溅射膜包括具有系数的第一材料 的热膨胀（CTE），其至少基本上等于衬底的CTE，以及具有大于衬底的热导率的导热性的第二材料。
-
129.发明申请Semiconductor Device Structures Incorporating Voids and Methods of Fabricating Such Structures 有权结合空隙的半导体器件结构和制造这种结构的方法公开(公告)号：US20070296039A1
公开(公告)日：2007-12-27
申请号：US11425588
申请日：2006-06-21
IPC分类号： H01L23/62
CPC分类号： H01L29/4983 , H01L21/823807 , H01L21/823864 , H01L29/4991 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor device structures and fabrication methods for field effect transistors in which a gate electrode is provided with an air gap or void disposed adjacent to a sidewall of the gate electrode. The void may be bounded by a dielectric spacer proximate to the sidewall of the gate electrode and a dielectric layer having a spaced relationship with the dielectric spacer. The methods of the invention involve the use of a temporary spacer consisting of a sacrificial material supplied adjacent to the sidewall of the gate electrode, which is removed after the dielectric layer is formed.
摘要翻译： 用于场效应晶体管的半导体器件结构和制造方法，其中栅电极设置有与栅电极的侧壁相邻设置的气隙或空隙。 空隙可以由靠近栅电极的侧壁的电介质隔离物和与电介质间隔物具有间隔关系的电介质层界定。 本发明的方法涉及使用由邻近栅电极的侧壁提供的牺牲材料组成的临时间隔物，其在形成介电层之后被去除。
-
公开(公告)号：US07265696B2
公开(公告)日：2007-09-04
申请号：US11272589
申请日：2005-11-10
IPC分类号： H03M1/10
CPC分类号： H03M1/1076
摘要： In a first aspect, a method of testing an analog circuit is provided. The method includes (1) providing the analog circuit with a screening circuit adapted to cause the analog circuit to function like a logic gate during a test; and (2) applying digital signals to the analog circuit to test the analog circuit at a wafer level so as to detect a defect in one or more components of the analog circuit. Numerous other aspects are provided.
-
-
-
-
-
-
-
-
-
搜索结果
163 条记录 (耗时 0.042 秒)