公开(公告)号：US06500709B2

公开(公告)日：2002-12-31

申请号：US09767480

申请日：2001-01-22

申请人： Kunal R. Parekh ,  John K. Zahurak

发明人： Kunal R. Parekh ,  John K. Zahurak

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L21/76895 ,  H01L27/10811 ,  H01L27/10855 ,  H01L28/84 ,  Y10S438/964

摘要： The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node. The invention also includes a DRAM cell comprising: a) a bitline node and a capacitor node electrically connected together through a transistor gate; b) a capacitor electrically connected to the capacitor node, the capacitor comprising; i) a storage node, the storage node in lateral cross-section comprising an outer surface extending over a top of the storage node, along a pair of opposing lateral surfaces of the storage node, and within laterally opposing cavities beneath the storage node; ii) a dielectric layer against the storage node outer surface and extending within the opposing cavities beneath the storage node; and iii) a cell plate layer against the dielectric layer and extending within the opposing cavities beneath the storage node; and c) a bitline electrically connected to the bitline node.

摘要翻译： 本发明包括DRAM结构，电容器结构，集成电路以及形成DRAM结构，集成电路和电容器结构的方法。 本发明包括一种形成电容器的方法，其中：a）形成第一层; b）在第一层上形成半导体材料掩蔽层; c）通过掩模层和第一层将一个开口蚀刻到一个节点上; d）存储节点层形成在所述开口内并与所述掩蔽层电连接; e）从掩蔽层和存储节点层形成电容器存储节点; 以及f）在电容器存储节点处可操作地形成电容器介电层和外部电容器板。 本发明还包括DRAM单元，其包括：a）通过晶体管栅极电连接在一起的位线节点和电容器节点; b）电连接到所述电容器节点的电容器，所述电容器包括： i）存储节点，所述存储节点在横截面中包括沿着所述存储节点的一对相对的侧表面延伸到所述存储节点的顶部的外表面，以及在所述存储节点下方的横向相对的空腔内; ii）抵靠存储节点外表面并在存储节点下面的相对空腔内延伸的电介质层; 以及iii）抵靠所述电介质层并且在所述存储节点下方的相对空腔内延伸的电池板层; 以及c）与所述位线节点电连接的位线。

公开(公告)号：US06486060B2

公开(公告)日：2002-11-26

申请号：US09146639

申请日：1998-09-03

申请人： Michael J. Hermes ,  Kunal R. Parekh

发明人： Michael J. Hermes ,  Kunal R. Parekh

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76889 ,  H01L21/823425 ,  H01L21/823475

摘要： A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitride spacers along each gate, a plurality of conductive plugs each contacting the wafer, and a BPSG layer overlying the transistor gates and contacting the active area. A portion of the BPSG layer is etched thereby exposing the TEOS caps. A portion of the BPSG layer remains on the active area after completion of the etch. Subsequently, a portion of the TEOS caps are removed to expose the transistor gates and a titanium silicide layer is formed simultaneously to contact the transistor gates and the plugs. An inventive structure resulting from the inventive process is also described.

摘要翻译： 一种用于形成半导体器件的方法包括以下步骤：提供半导体衬底组件，其包括其中形成有有效区的半导体晶片，每个具有TEOS帽的多个晶体管栅极和沿着每个栅极的一对氮化物间隔物，多个 每个接触晶片的导电插塞和覆盖晶体管栅极并接触有源区的BPSG层。 BPSG层的一部分被蚀刻，从而暴露TEOS帽。 完成蚀刻后，BPSG层的一部分保留在有源区上。 随后，去除TEOS帽的一部分以暴露晶体管栅极，同时形成钛硅化物层以接触晶体管栅极和插塞。 还描述了由本发明方法产生的创造性结构。

公开(公告)号：US06482707B1

公开(公告)日：2002-11-19

申请号：US09532094

申请日：2000-03-21

申请人： Mark Fischer ,  Charles H. Dennison ,  Fawad Ahmed ,  Richard H. Lane ,  John K. Zahurak ,  Kunal R. Parekh

发明人： Mark Fischer ,  Charles H. Dennison ,  Fawad Ahmed ,  Richard H. Lane ,  John K. Zahurak ,  Kunal R. Parekh

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28247 ,  H01L29/6656

摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.

摘要翻译： 公开了一种用于在诸如MOSFET访问装置的存储器阵列器件中形成扩散区的双层覆盖离子注入方法。 该方法提供了在其表面上形成栅极结构的半导体衬底。接下来，通过第一覆盖离子注入工艺在与沟道区相邻的区域中形成第一对扩散区。 第一次毯式离子注入工艺具有第一能级和剂量。 该器件经受氧化条件，其在栅极结构上形成氧化的侧壁。 在与第一离子注入工艺相同的位置处进行第二覆盖离子注入工艺，向扩散区域添加额外的掺杂剂。 第二次毯子离子注入过程具有第二能量水平和剂量。 所得到的扩散区域提供了比现有技术的装置更好的静态刷新性能的装置。 此外，第一和第二能量水平和剂量基本上低于现有技术单一植入过程中使用的能级和剂量。

公开(公告)号：US06468859B1

公开(公告)日：2002-10-22

申请号：US09399592

申请日：1999-09-20

申请人： Kunal R. Parekh ,  Charles H. Dennison ,  Jeffrey W. Honeycutt

发明人： Kunal R. Parekh ,  Charles H. Dennison ,  Jeffrey W. Honeycutt

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L21/76802 ,  H01L21/76834 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91 ,  Y10S438/964

摘要： A stress buffer and dopant barrier in the form of a TetraEthylOrthoSilicate (TEOS) film is deposited after the capacitor cell plate has been etched and cleaned to thereby eliminate electrical shorts from the bit line to the cell plate.

摘要翻译： 在电容器电池板被蚀刻和清洁之后，沉积出四乙基正硅酸盐（TEOS）形式的应力缓冲器和掺杂剂阻挡层，从而消除从位线到电池板的电短路。

公开(公告)号：US06410951B1

公开(公告)日：2002-06-25

申请号：US09822249

申请日：2001-04-02

申请人： Mark Fischer ,  Charles H. Dennison ,  Fawad Ahmed ,  Richard H. Lane ,  John K. Zahurak ,  Kunal R. Parekh

发明人： Mark Fischer ,  Charles H. Dennison ,  Fawad Ahmed ,  Richard H. Lane ,  John K. Zahurak ,  Kunal R. Parekh

IPC分类号： H01L21336

摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface. Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.

公开(公告)号：US06406977B2

公开(公告)日：2002-06-18

申请号：US09521095

申请日：2000-03-07

申请人： David L. Dickerson ,  Richard H. Lane ,  Charles H. Dennison ,  Kunal R. Parekh ,  Mark Fischer ,  John K. Zahurak

发明人： David L. Dickerson ,  Richard H. Lane ,  Charles H. Dennison ,  Kunal R. Parekh ,  Mark Fischer ,  John K. Zahurak

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  H01L21/0332 ,  H01L21/76235

摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.

摘要翻译： 一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。 另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。

公开(公告)号：US06383868B1

公开(公告)日：2002-05-07

申请号：US09653501

申请日：2000-08-31

申请人： Kunal R. Parekh ,  John K. Zahurak

发明人： Kunal R. Parekh ,  John K. Zahurak

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L27/10811 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/90

摘要： Methods for forming contact structures and container structures, as well as integrated circuits that can be formed by employing those methods are provided. The integrated circuitry formed by the methods of the present invention provide capacitors in containers having sufficiently high storage capacitance for advanced integrated circuit devices. In addition the methods for forming such container capacitors facilitate the formation of contacts structures and provided for the formation of local interconnect structures and electrical contact to each of the structures formed.

摘要翻译： 提供形成接触结构和容器结构的方法以及可以通过采用这些方法形成的集成电路。 通过本发明的方法形成的集成电路为先进的集成电路器件提供具有足够高的存储电容的容器中的电容器。 此外，用于形成这种容器电容器的方法有助于形成接触结构并且提供用于形成局部互连结构和与形成的每个结构的电接触。

公开(公告)号：US06329682B1

公开(公告)日：2001-12-11

申请号：US09526559

申请日：2000-03-16

申请人： Kunal R. Parekh ,  John K. Zahurak

发明人： Kunal R. Parekh ,  John K. Zahurak

IPC分类号： H01L27108

CPC分类号： H01L27/10844 ,  H01L27/10852 ,  Y10S257/906

摘要： A stacked capacitor memory cell and method for its fabrication including providing a layer of insulation glass over word lines on a silicon semiconductor substrate; self-aligning contact holes at the storage nodes and bit line contact location; providing a blanket layer of polysilicon, then silicide, and then an insulating cap; removing a portion of the insulating cap, silicide and polysilicon to form polysilicon plugs having outward surfaces at an elevation below the surface of the insulating glass, thus forming the bit line, a bit line contact and isolating the storage nodes; and providing a stacked capacitor on top of the bit line and in electrical communication with the storage node contact location through the plugs formed simultaneously with the bit line and bit line contact.

摘要翻译： 一种叠层电容器存储单元及其制造方法，包括在硅半导体衬底上的字线上提供绝缘玻璃层; 存储节点和位线接触位置处的自对准接触孔; 提供覆盖层的多晶硅，然后是硅化物，然后是绝缘帽; 去除绝缘帽，硅化物和多晶硅的一部分以形成在绝缘玻璃表面下方的外表面的多晶硅塞，从而形成位线，位线接触并隔离存储节点; 并且在位线顶部提供堆叠的电容器，并通过与位线和位线接触同时形成的插头与存储节点接触位置电连通。

公开(公告)号：US06228710B1

公开(公告)日：2001-05-08

申请号：US09291423

申请日：1999-04-13

申请人： Kunal R. Parekh ,  John K. Zahurak

发明人： Kunal R. Parekh ,  John K. Zahurak

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/10811 ,  H01L27/10888 ,  H01L28/84 ,  H01L28/87

摘要： The invention encompasses methods of forming DRAM constructions, methods of forming capacitor constructions, DRAM constructions, and capacitor constructions. The invention includes a method in which a) a first layer is formed over a node location; b) a semiconductive material masking layer is formed over the first layer; c) an opening is formed through the semiconductive material masking layer and the first layer to the node location; d) an upwardly open capacitor storage node layer is formed within the opening; e) a storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and a capacitor plate are formed over the storage node. The invention also includes a capacitor structure comprising: a) an insulative layer over a substrate; b) a polysilicon layer over the insulative layer; c) an opening extending through the polysilicon layer and the insulative layer to a node, the opening comprising an upper portion and a lower portion, the upper portion comprising a first minimum cross-sectional dimension and the lower portion comprising a second minimum cross-sectional dimension which is narrower than the first minimum cross-sectional dimension, the opening further comprising a step at an interface of the upper and lower portions; d) a spacer over the step; e) a storage node layer over the spacer, polysilicon layer and the node; and f) a dielectric layer and a cell plate layer capacitively coupled to the storage node layer.

摘要翻译： 本发明包括形成DRAM结构的方法，形成电容器结构的方法，DRAM结构和电容器结构。 本发明包括一种方法，其中a）在节点位置上形成第一层; b）在第一层上形成半导体材料掩蔽层; c）通过半导体材料掩蔽层和第一层到达节点位置形成开口; d）在开口内形成向上开放的电容器存储节点层; e）从掩蔽层和存储节点层形成存储节点; 以及f）在所述存储节点上形成电容器介电层和电容器板。 本发明还包括电容器结构，包括：a）衬底上的绝缘层; b）绝缘层上的多晶硅层; c）延伸穿过所述多晶硅层和所述绝缘层到达节点的开口，所述开口包括上部和下部，所述上部包括第一最小横截面尺寸，并且所述下部包括第二最小横截面 尺寸比第一最小横截面尺寸窄，该开口还包括在上部和下部的界面处的台阶; d）台阶上的间隔物; e）在所述间隔物，多晶硅层和所述节点之上的存储节点层; 以及f）电容耦合到存储节点层的电介质层和电池板层。

公开(公告)号：US06174785B1

公开(公告)日：2001-01-16

申请号：US09099274

申请日：1998-06-18

申请人： Kunal R. Parekh ,  Li Li

发明人： Kunal R. Parekh ,  Li Li

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  Y10S148/05

摘要： Shallow trench isolation regions in a semiconductor device are formed by utilizing sacrificial spacers such as polysilicon spacers having a rounded shape to form trench isolation areas. The spacer shape is transferred into a semiconductor substrate during an etching process to define the profile of the trench, resulting in a trench with substantially rounded upper and lower corners in the substrate. An oxide filler material is deposited in the trench and over the substrate to form a covering layer. The covering layer is then polished back to form a filled trench region which electrically isolates active areas in the substrate. The polishing step can be performed by a blanket dry etching procedure, or by a combination of chemical/mechanical planarization and wet etching. The rounded shape of the trench improves the electrical characteristics of the trench such that current leakage is decreased, and also provides a more optimized trench profile for filling the trench with the filler material.

摘要翻译： 通过利用诸如具有圆形形状的多晶硅间隔物之类的牺牲隔离物形成沟槽隔离区域，形成半导体器件中的浅沟槽隔离区域。 在蚀刻过程期间将间隔物形状转移到半导体衬底中以限定沟槽的轮廓，从而产生在衬底中具有基本上圆形的上角和下角的沟槽。 氧化物填充材料沉积在沟槽中并在衬底上沉积以形成覆盖层。 然后将覆盖层回抛以形成电绝缘衬底中的有源区域的填充沟槽区域。 抛光步骤可以通过橡皮干蚀刻方法，或通过化学/机械平面化和湿蚀刻的组合进行。 沟槽的圆形形状改善了沟槽的电气特性，使得电流泄漏减小，并且还提供了用填充材料填充沟槽的更优化的沟槽轮廓。