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公开(公告)号：US20100039191A1
公开(公告)日：2010-02-18
申请号：US12191519
申请日：2008-08-14
申请人： Louis Lu-Chen Hsu , Jong-Ru Guo , Ping-Chuan Wang , Zhijian Yang
发明人： Louis Lu-Chen Hsu , Jong-Ru Guo , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H03H11/48
摘要： An apparatus and method for manufacturing low-cost high-density compact active inductor module using existing DRAM, SRAM and logic process integration. The elements of the active inductor modules are formed by three semiconductor devices including nMOS devices, deep-trench capacitors and a polysilicon or TaN resistor. The active inductor modules can be connected in a parallel and/or serial configuration to obtain a wide range of inductance values. The modular active inductors can be advantageously stored in an ASIC library to facilitate a flexible and convenient circuit design.
摘要翻译： 一种使用现有DRAM，SRAM和逻辑处理集成制造低成本高密度紧凑型有源电感模块的装置和方法。 有源电感器模块的元件由包括nMOS器件，深沟槽电容器和多晶硅或TaN电阻器的三个半导体器件形成。 有源电感模块可以并联和/或串联配置连接，以获得宽范围的电感值。 模块化有源电感器可以有利地存储在ASIC库中，以便于灵活和方便的电路设计。
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122.发明授权公开(公告)号：US07659599B2
公开(公告)日：2010-02-09
申请号：US12049258
申请日：2008-03-14
IPC分类号： H01L29/00
CPC分类号： H01L21/76243
摘要： In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.
摘要翻译： 在一方面，提供了一种用于形成绝缘体上硅（SOI）层的方法。 该方法包括以下步骤：（1）提供硅衬底; （2）使用低注入能量用氧选择性地注入硅衬底以形成超薄图案种子层; 和（3）使用超薄图案种子层在硅衬底上形成图案化SOI层。 提供了许多其他方面。
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公开(公告)号：US07659168B2
公开(公告)日：2010-02-09
申请号：US11266740
申请日：2005-11-03
IPC分类号： H01L21/336
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： In a first aspect, a first apparatus is provided. The first apparatus is an eFuse including (1) a semiconducting layer above an insulating oxide layer of a substrate; (2) a diode formed in the semiconducting layer; and (3) a silicide layer formed on the diode. Numerous other aspects are provided.
摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是eFuse，包括（1）衬底的绝缘氧化物层上方的半导体层; （2）形成在半导体层中的二极管; 和（3）二极管上形成的硅化物层。 提供了许多其他方面。
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124.发明授权公开(公告)号：US07645645B2
公开(公告)日：2010-01-12
申请号：US11372334
申请日：2006-03-09
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside at different heights relative to a supporting surface of the fuse structure, and the interconnecting fuse element transitions between the different heights of the first terminal portion and the second terminal portion. The first and second terminal portions are oriented parallel to the supporting surface, while the fuse element includes a portion oriented orthogonal to the supporting surface, and includes at least one right angle bend where transitioning from at least one of the first and second terminal portions to the orthogonal oriented portion of the fuse element.
摘要翻译： 提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分相对于熔丝结构的支撑表面驻留在不同的高度处，并且互连熔丝元件在第一端子部分和第二端子部分的不同高度之间转变。 第一端子部分和第二端子部分平行于支撑表面定向，而熔丝元件包括垂直于支撑表面定向的部分，并且包括至少一个直角弯曲部，其从第一和第二端子部分中的至少一个过渡到 保险丝元件的正交取向部分。
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公开(公告)号：US07624289B2
公开(公告)日：2009-11-24
申请号：US11949129
申请日：2007-12-03
CPC分类号： H01L23/50 , H01H59/0009 , H01L2924/0002 , H01L2924/3011 , Y10T307/469 , H01L2924/00
摘要： A structure and method for power distribution to a network for an integrated circuit chip complex are provided. The chip complex has at least two sectors, each having at least one power providing connection with at least one of said connections beings individually addressable by, and isolatable from, a given power source. At least one MEMS is positioned to selectively connect and disconnect said at least one connection to and from said given power source.
摘要翻译： 提供了一种用于集成电路芯片复合体的网络配电的结构和方法。 芯片复合体具有至少两个扇区，每个扇区具有至少一个功率提供与至少一个所述连接体的连接，所述至少一个所述连接体可以由给定的电源单独寻址并且可与其隔离。 至少一个MEMS被定位成选择性地将所述至少一个连接与所述给定电源连接和断开。
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126.发明授权Design structure for an automatic driver/transmission line/receiver impedance matching circuitry 失效自动驱动/传输线路/接收机阻抗匹配电路的设计结构公开(公告)号：US07622946B2
公开(公告)日：2009-11-24
申请号：US11934825
申请日：2007-11-05
IPC分类号： H03K17/16 , H03K19/003 , H03L7/06
CPC分类号： H03K19/0005 , H03J3/185 , H03L7/08 , H03L7/0805 , H03L7/0891
摘要： A design structure for an impedance matcher that automatically matches impedance between a driver and a receiver. The design structure for an impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The impedance matcher also includes tunable impedance matching circuitry responsive to one or more voltage-controlled oscillator control signals within the PLL circuit so as to generate an output signal that is impedance matched with the receiver.
摘要翻译： 用于阻抗匹配器的设计结构，其自动匹配驱动器和接收器之间的阻抗。 阻抗匹配器的设计结构包括锁定到由驱动器提供的数据信号的锁相环（PLL）电路。 阻抗匹配器还包括响应于PLL电路内的一个或多个压控振荡器控制信号的可调阻抗匹配电路，以便产生与接收器阻抗匹配的输出信号。
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公开(公告)号：US07471101B2
公开(公告)日：2008-12-30
申请号：US11942241
申请日：2007-11-19
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , H01L21/76886 , H01L2924/0002 , H04B7/0814 , H01L2924/00
摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.
摘要翻译： 公开了用于控制电迁移的系统和方法，并减少其有害影响。 实施例提供了当指示电迁移程度的测量指示操作的愈合周期是有必要的时将施加的电压反转到集成电路。 在愈合周期中，集成电路的电路正常工作，但电迁移效应相反。 在一个实施例中，微电子机械开关设置在最低级别的金属化处，以将电流方向切换到集成电路的金属化水平。 在另一个实施例中，如果指示电迁移程度的测量超过参考电平达指定量，则施加到集成电路的电压的极性反转，导致电流切换方向以对抗电迁移。 提供多个开关以切换电流方向通过最低金属化水平，使得即使施加的电压的极性已经被反转，电路也能正常工作。
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公开(公告)号：US07305571B2
公开(公告)日：2007-12-04
申请号：US10940543
申请日：2004-09-14
CPC分类号： H01L23/50 , H01H59/0009 , H01L2924/0002 , H01L2924/3011 , Y10T307/469 , H01L2924/00
摘要： A structure and method for power distribution to a network for an integrated circuit chip complex are provided. The chip complex has at least two sectors, each having at least one power providing connection with at least one of said connections beings individually addressable by, and isolatable from, a given power source. At least one MEMS is positioned to selectively connect and disconnect said at least one connection to and from said given power source.
摘要翻译： 提供了一种用于集成电路芯片复合体的网络配电的结构和方法。 芯片复合体具有至少两个扇区，每个扇区具有至少一个功率提供与至少一个所述连接体的连接，所述至少一个所述连接体可以由给定的电源单独寻址并且可与其隔离。 至少一个MEMS被定位成选择性地将所述至少一个连接与所述给定电源连接和断开。
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129.发明授权公开(公告)号：US06674673B1
公开(公告)日：2004-01-06
申请号：US10064867
申请日：2002-08-26
IPC分类号： G11C700
CPC分类号： G11C29/846 , G11C2207/104
摘要： A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.
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130.发明授权Method of producing dynamic random access memory (DRAM) cell with folded bitline vertical transistor 失效具有折叠位线垂直晶体管的动态随机存取存储器（DRAM）单元的制造方法公开(公告)号：US06399447B1
公开(公告)日：2002-06-04
申请号：US09619671
申请日：2000-07-19
IPC分类号： H01L21336
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device and a method for forming the semiconductor device, include forming a mandrel, forming spacer wordline conductors on sidewalls of the mandrel, separating, by using a trim mask, adjacent spacer wordline conductors, and providing a contact area to contact alternating ones of pairs of the spacer wordline conductors.
摘要翻译： 半导体器件和用于形成半导体器件的方法包括形成心轴，在心轴的侧壁上形成间隔物字线导体，通过使用修剪掩模分离相邻间隔物字线导体，并提供接触区域以接触交替的 一对间隔字线导线。
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