公开(公告)号：US08846488B2

公开(公告)日：2014-09-30

申请号：US13578598

申请日：2011-11-30

申请人： Qingqing Liang ,  Huaxiang Yin ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huaxiang Yin ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L21/76 ,  H01L29/78 ,  H01L21/762 ,  H01L21/265

CPC分类号： H01L21/76224 ,  H01L21/26506 ,  H01L29/7842 ,  H01L29/7847

摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device.

摘要翻译： 本发明涉及半导体器件及其制造方法。 根据本发明的实施例的半导体器件可以包括：衬底; 位于所述基板上的器件区域; 以及至少一个应力引入区域，其通过隔离结构从所述器件区域分离，其中所述应力引入所述至少一个应力引入区域的至少一部分，其中所述应力引入所述至少一个应力的至少一部分 引入区域通过利用激光照射包含在至少一个应力导入区域中的非晶化部分以使非晶化部分重结晶而产生。 根据本发明的实施例的半导体器件以更简单的方式产生应力，从而提高器件的性能。

公开(公告)号：US08802533B1

公开(公告)日：2014-08-12

申请号：US13989297

申请日：2012-07-30

申请人： Changliang Qin ,  Huaxiang Yin

发明人： Changliang Qin ,  Huaxiang Yin

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7833 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A transistor device comprising epitaxial LDD and Halo regions and a method of manufacturing the same are disclosed. According to embodiments of the present disclosure, the method may comprise: forming a gate stack on a semiconductor substrate; forming a gate spacer which covers the top of the gate stack and sidewalls of the gate stack; forming source/drain grooves; epitaxially growing a Halo material layer in the source/drain grooves, wherein the Halo material layer has a first doping element therein; epitaxially growing source/drain regions which apply stress to a channel region of the device, wherein the source/drain regions have a second doping element, opposite in conductivity to the first doping element, therein; isotropically etching the source/drain regions to remove portions of the source/drain regions, wherein the etching also removes portions of the Halo material layer directly under the gate spacer and extends to the channel region to some extent, wherein remaining portions of the Halo material layer constitute Halo regions of the device; and epitaxially growing an LDD material layer to form LDD regions of the device.

摘要翻译： 公开了一种包括外延LDD和Halo区域的晶体管器件及其制造方法。 根据本公开的实施例，该方法可以包括：在半导体衬底上形成栅极堆叠; 形成覆盖栅极堆叠的顶部和栅极叠层的侧壁的栅极间隔物; 形成源极/漏极沟槽; 在源极/漏极沟槽中外延生长Halo材料层，其中Halo材料层在其中具有第一掺杂元素; 外延生长的源极/漏极区域，其对器件的沟道区域施加应力，其中源极/漏极区域具有与第一掺杂元件的导电性相反的第二掺杂元素; 各向同性蚀刻源/漏区以去除源极/漏极区的部分，其中蚀刻还将栅极间隔物正下方的Halo材料层的部分去除并在一定程度上延伸到沟道区，其中Halo材料的剩余部分 层构成设备的光晕区域; 并外延生长LDD材料层以形成器件的LDD区域。

公开(公告)号：US08748272B2

公开(公告)日：2014-06-10

申请号：US13318344

申请日：2011-04-20

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Cheng

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Cheng

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8238

CPC分类号： H01L29/7845 ,  H01L21/26506 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

摘要： The present invention relates to a method of introducing strain into a channel and a device manufactured by using the method, the method comprising: providing a semiconductor substrate; forming a channel in the semiconductor substrate; forming a first gate dielectric layer on the channel; forming a polysilicon gate layer on the first gate dielectric layer; doping or implanting a first element into the polysilicon gate layer; removing a part of the first gate dielectric layer and polysilicon gate layer to thereby form a first gate structure; forming a source/drain extension region in the channel; forming spacers on both sides of the first gate structure; forming a source/drain in the channel; and performing annealing such that lattice change occurs in the polysilicon that is doped or implanted with the first element in the high-temperature crystallization process, thereby producing a first strain in the polysilicon gate layer, and introducing the first strain through the gate dielectric layer to the channel. This method has greater process flexibility and simple process complexity with no additional process cost.

摘要翻译： 本发明涉及将应变引入通道的方法和使用该方法制造的器件，该方法包括：提供半导体衬底; 在半导体衬底中形成通道; 在所述通道上形成第一栅介质层; 在所述第一栅极介电层上形成多晶硅栅极层; 将第一元件掺杂或注入到多晶硅栅极层中; 去除所述第一栅极介电层和多晶硅栅极层的一部分，从而形成第一栅极结构; 在通道中形成源极/漏极延伸区域; 在第一栅极结构的两侧形成间隔物; 在通道中形成源极/漏极; 并且进行退火，使得在高温结晶工艺中掺杂或注入第一元素的多晶硅中发生晶格变化，从而在多晶硅栅极层中产生第一应变，并将第一应变通过栅极介电层引入到 这个频道。 该方法具有更大的工艺灵活性和简单的工艺复杂性，无需额外的工艺成本

公开(公告)号：US20140057404A1

公开(公告)日：2014-02-27

申请号：US13989164

申请日：2012-07-31

申请人： Changliang Qin ,  Peizhen Hong ,  Huaxiang Yin

发明人： Changliang Qin ,  Peizhen Hong ,  Huaxiang Yin

IPC分类号： H01L21/306 ,  H01L29/66

CPC分类号： H01L21/30604 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate; etching the substrate on both sides of the gate stack to form C-shaped source/drain grooves; and wet-etching the C-shaped source/drain grooves to form Σ-shaped source/drain grooves. With this method, it is possible to effectively increase stress applied to a channel region, to accurately control a depth of the source/drain grooves, and to reduce roughness of side walls and bottom portions of the grooves and thus reduce defects by etching the C-shaped source/drain grooves and then further wet-etching them to form the Σ-shaped source/drain grooves.

摘要翻译： 公开了制造半导体器件的方法。 在一个实施例中，该方法包括：在衬底上形成栅叠层; 在栅极堆叠的两侧蚀刻衬底以形成C形源极/漏极沟槽; 并对C形源极/漏极沟槽进行湿蚀刻以形成Σ型源极/漏极沟槽。 通过该方法，能够有效地增加施加于沟道区域的应力，精确地控制源极/漏极沟槽的深度，并且可以减小沟槽的侧壁和底部的粗糙度，从而通过蚀刻C来减少缺陷 形状的源极/漏极沟槽，然后进一步湿法蚀刻它们以形成Sigma形状的源极/漏极沟槽。

公开(公告)号：US20140015068A1

公开(公告)日：2014-01-16

申请号：US13699731

申请日：2012-07-24

申请人： Hong Yang ,  Wenwu Wang ,  Huaxiang Yin ,  Jiang Yan ,  Xueli Ma

发明人： Hong Yang ,  Wenwu Wang ,  Huaxiang Yin ,  Jiang Yan ,  Xueli Ma

IPC分类号： H01L29/49 ,  H01L21/28

CPC分类号： H01L29/495 ,  H01L21/28008 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： The disclosure relates to a gate structure, a semiconductor device and methods for forming the same. An embodiment of the disclosure provides a method for forming a gate structure, including: providing a substrate; forming an interface layer on the substrate; forming a gate dielectric layer on the interface layer; forming a gate dielectric capping layer on the gate dielectric layer; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming an oxygen scavenging element capping layer on the oxygen scavenging element layer; performing Post-Metallization Annealing; performing etching until the etching stop layer is exposed; forming a work function adjustment layer on the etching stop layer; and forming a gate layer on the work function adjustment layer.

摘要翻译： 本公开涉及一种栅极结构，半导体器件及其形成方法。 本公开的实施例提供了一种用于形成栅极结构的方法，包括：提供基板; 在衬底上形成界面层; 在界面层上形成栅介电层; 在所述栅极电介质层上形成栅介电覆盖层; 在所述栅极电介质覆盖层上形成蚀刻停止层; 在所述蚀刻停止层上形成氧清除元件层; 在除氧元件层上形成氧清除元件盖层; 执行金属后退火; 进行蚀刻，直到蚀刻停止层露出为止; 在所述蚀刻停止层上形成功函数调整层; 以及在所述功函数调整层上形成栅极层。

公开(公告)号：US20140015063A1

公开(公告)日：2014-01-16

申请号：US13699734

申请日：2012-07-24

申请人： Hong Yang ,  Xueli Ma ,  Wenwu Wang ,  Kai Han ,  Xiaolei Wang ,  Huaxiang Yin ,  Jiang Yan

发明人： Hong Yang ,  Xueli Ma ,  Wenwu Wang ,  Kai Han ,  Xiaolei Wang ,  Huaxiang Yin ,  Jiang Yan

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/8238 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

摘要： A method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on the substrate; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming a first work function adjustment layer on the oxygen scavenging element layer; etching the first work function adjustment layer above the nMOSFET area; forming a second work function adjustment layer on the surface of the substrate; metal layer depositing and annealing to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.

摘要翻译： 一种用于形成栅极结构的方法，包括：提供衬底，其中所述衬底包括nMOSFET区域和pMOSFET区域，nMOSFET区域和pMOSFET区域中的每一个具有栅极沟槽，并且每个栅极沟槽设置在 底部具有栅极电介质层; 在所述衬底上形成栅介电覆盖层; 在所述栅极电介质覆盖层上形成蚀刻停止层; 在所述蚀刻停止层上形成氧清除元件层; 在除氧元件层上形成第一功函数调整层; 蚀刻nMOSFET区域上方的第一功函数调整层; 在所述基板的表面上形成第二功函数调整层; 金属层沉积和退火以用金属层填充栅极沟槽; 以及去除栅极沟槽外的金属层。

公开(公告)号：US20140015062A1

公开(公告)日：2014-01-16

申请号：US13699732

申请日：2012-07-24

申请人： Hong Yang ,  Xueli Ma ,  Wenwu Wang ,  Kai Han ,  Xiaolei Wang ,  Huaxiang Yin ,  Jiang Yan

发明人： Hong Yang ,  Xueli Ma ,  Wenwu Wang ,  Kai Han ,  Xiaolei Wang ,  Huaxiang Yin ,  Jiang Yan

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L27/092

摘要： An embodiment of the present disclosure provides a method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on a surface of the substrate; forming an oxygen scavenging element layer on the gate dielectric capping layer; forming an etching stop layer on the oxygen scavenging element layer; forming a work function adjustment layer on the etching stop layer; performing metal layer deposition and annealing process to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.

摘要翻译： 本公开的实施例提供了一种用于形成栅极结构的方法，包括：提供衬底，其中衬底包括nMOSFET区域和pMOSFET区域，nMOSFET区域和pMOSFET区域中的每一个具有栅极沟槽，并且 栅极沟槽在底部设置有栅极电介质层; 在所述衬底的表面上形成栅介电覆盖层; 在所述栅介质顶盖层上形成氧清除元件层; 在除氧元件层上形成蚀刻停止层; 在所述蚀刻停止层上形成功函数调整层; 执行金属层沉积和退火工艺以用金属层填充栅极沟槽; 以及去除栅极沟槽外的金属层。

公开(公告)号：US08445332B2

公开(公告)日：2013-05-21

申请号：US11976009

申请日：2007-10-19

申请人： Wenxu Xianyu ,  Young-soo Park ,  Hans S. Cho ,  Huaxiang Yin ,  Hyuck Lim

发明人： Wenxu Xianyu ,  Young-soo Park ,  Hans S. Cho ,  Huaxiang Yin ,  Hyuck Lim

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： C30B29/06 ,  C30B13/24 ,  C30B25/02 ,  C30B29/60 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/02675 ,  H01L29/42392 ,  H01L29/78696 ,  Y10T428/2962

摘要： A method of fabricating a single crystal silicon rod may include forming an insulation layer on a substrate, forming a hole in the insulation layer, selectively growing silicon in the hole, forming a silicon layer on the hole and on the insulation layer, forming a rod pattern on the silicon layer in a direction that is non-radial with respect to the hole, and melting the silicon layer and crystallizing the silicon layer by illuminating a laser beam on the silicon layer where the rod pattern is formed to generate a nucleation site at a position corresponding to the hole. According to the method, a single crystal silicon rod having no defects may be formed.

摘要翻译： 制造单晶硅棒的方法可以包括在衬底上形成绝缘层，在绝缘层中形成孔，选择性地生长孔中的硅，在孔和绝缘层上形成硅层，形成棒 在相对于孔的非径向的方向上在硅层上形成图案，并且通过照射形成棒图案的硅层上的激光束来熔化硅层并使硅层结晶，从而在硅层上产生成核位置 对应于孔的位置。 根据该方法，可以形成没有缺陷的单晶硅棒。

公开(公告)号：US20130093041A1

公开(公告)日：2013-04-18

申请号：US13578598

申请日：2011-11-30

申请人： Qingqing Liang ,  Huaxiang Yin ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huaxiang Yin ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/26506 ,  H01L29/7842 ,  H01L29/7847

摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device.

摘要翻译： 本发明涉及半导体器件及其制造方法。 根据本发明的实施例的半导体器件可以包括：衬底; 位于所述基板上的器件区域; 以及至少一个应力引入区域，其通过隔离结构从所述器件区域分离，其中所述应力引入所述至少一个应力引入区域的至少一部分，其中所述应力引入所述至少一个应力的至少一部分 引入区域通过利用激光照射包含在至少一个应力导入区域中的非晶化部分以使非晶化部分重结晶而产生。 根据本发明的实施例的半导体器件以更简单的方式产生应力，从而提高器件的性能。

公开(公告)号：US08309404B2

公开(公告)日：2012-11-13

申请号：US13173128

申请日：2011-06-30

申请人： Huaxiang Yin ,  Takashi Noguchi ,  Hyuk Lim ,  Wenxu Xianyu ,  Hans S. Cho

发明人： Huaxiang Yin ,  Takashi Noguchi ,  Hyuk Lim ,  Wenxu Xianyu ,  Hans S. Cho

IPC分类号： H01L21/84

CPC分类号： H01L27/12 ,  H01L29/78609 ,  H01L29/78696

摘要： A thin film transistor comprises an Si-based channel having a nonlinear electron-moving path, a source and a drain disposed at both sides of the channel, a gate disposed above the channel, an insulator interposed between the channel and the gate, and a substrate supporting the channel and the source and the drain disposed at either side of the channel respectively.

摘要翻译： 薄膜晶体管包括具有非线性电子移动路径的Si基通道，设置在沟道两侧的源极和漏极，设置在沟道上方的栅极，介于通道和栅极之间的绝缘体，以及 支撑通道的基板，分别设置在通道的两侧的源极和漏极。