公开(公告)号：US20200250115A1

公开(公告)日：2020-08-06

申请号：US16775679

申请日：2020-01-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christoph Raisch ,  Marco Kraemer ,  Frank Siegfried Lehnert ,  Matthias Klein ,  Jonathan D. Bradbury ,  Christian Jacobi ,  Peter Dana Driever ,  Brenton Belmar

IPC: G06F13/16 ,  G06F9/30

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.

公开(公告)号：US20200249944A1

公开(公告)日：2020-08-06

申请号：US16775784

申请日：2020-01-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christoph Raisch ,  Marco Kraemer ,  Frank Siegfried Lehnert ,  Matthias Klein ,  Jonathan D. Bradbury ,  Christian Jacobi ,  Brenton Belmar ,  Peter Dana Driever

IPC: G06F9/30 ,  G06F11/07 ,  G06F9/54 ,  G06F11/30 ,  G06F11/14

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers. The system firmware includes a retry buffer and the core includes an analysis and retry logic.

公开(公告)号：US10587284B2

公开(公告)日：2020-03-10

申请号：US15948678

申请日：2018-04-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony T. Sofia ,  Matthias Klein ,  Jonathan D. Bradbury ,  Peter Sutton

IPC: H03M7/34 ,  H03M7/30 ,  G06F9/38 ,  G06F15/173

Abstract: A computer system includes a plurality of hardware processors, and a hardware accelerator. A first processor among the plurality of processor runs an application that issues a data compression request to compress or decompress a data stream. The hardware accelerator selectively operates in different modes to compresses or decompresses the data stream. Based on a selected mode, the hardware accelerator can utilize a different number of processors among the plurality of hardware to compress or decompress the data stream.

公开(公告)号：US10529396B2

公开(公告)日：2020-01-07

申请号：US15629923

申请日：2017-06-22

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Sascha Junghans ,  Matthias Klein ,  Pak-Kin Mak ,  Robert J. Sonnelitter, III ,  Chad G. Wilson

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C8/06

Abstract: A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.

公开(公告)号：US20190312587A1

公开(公告)日：2019-10-10

申请号：US15948678

申请日：2018-04-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony T. Sofia ,  Matthias Klein ,  Jonathan D. Bradbury ,  Peter Sutton

IPC: H03M7/30 ,  G06F15/173 ,  G06F9/38

Abstract: A computer system includes a plurality of hardware processors, and a hardware accelerator. A first processor among the plurality of processor runs an application that issues a data compression request to compress or decompress a data stream. The hardware accelerator selectively operates in different modes to compresses or decompresses the data stream. Based on a selected mode, the hardware accelerator can utilize a different number of processors among the plurality of hardware to compress or decompress the data stream.

公开(公告)号：US10423546B2

公开(公告)日：2019-09-24

申请号：US15806407

申请日：2017-11-08

Applicant: International Business Machines Corporation

Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Girish G. Kurup

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/28 ,  G06F13/42

Abstract: A method for coupling transactions with a configurable ordering controller in a computer system. The method comprises sending, by a coupling device, first data packets with an unordered attribute being set to an ordering controller. The method further comprises sending, by the coupling device, second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The method further comprises sending, by the ordering controller, the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.

公开(公告)号：US20180365180A1

公开(公告)日：2018-12-20

申请号：US15623429

申请日：2017-06-15

Applicant: International Business Machines Corporation

Inventor： David F. Craddock ,  Sascha Junghans ,  Matthias Klein ,  Eric N. Lais

IPC: G06F13/28 ,  G06F12/1027 ,  G06F13/42 ,  G06F12/1009 ,  G06F12/1081

CPC classification number: G06F13/28 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081 ,  G06F13/4282

Abstract: Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.

公开(公告)号：US10133691B2

公开(公告)日：2018-11-20

申请号：US15190262

申请日：2016-06-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Scott A. Brewer ,  David F. Craddock ,  Matthew J. Kalos ,  Matthias Klein ,  Eric N. Lais

IPC: G06F13/16 ,  G06F13/28 ,  G06F12/08 ,  G06F12/0868 ,  G06F12/0815 ,  G06F12/0886

Abstract: A computer-implemented method for synchronous input/output (I/O) cache line padding is described. The cache line padding occurs between a server having a processor executing an operating system and a recipient control unit. The method can include receiving, via the processor at the recipient control unit, a partial line direct memory access (DMA) write request; fetching, via the processor, a device table entry (DTE) associated with the partial line DMA write request; determining, via the processor, a cache line size for a synchronous input/output (I/O) cache line; and writing a full cache line DMA write request by padding, via the processor, the partial line DMA write request with a padded portion, where the padded portion is based on the cache line size.

公开(公告)号：US20180095887A1

公开(公告)日：2018-04-05

申请号：US15281690

申请日：2016-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David Craddock ,  Matthias Klein ,  Eric N. Lais ,  Harry M. Yudenfriend

IPC: G06F12/0891 ,  G06F11/10 ,  G06F12/126

CPC classification number: G06F11/1004 ,  G06F12/0875 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/126 ,  G06F2212/1008 ,  G06F2212/1041 ,  G06F2212/40 ,  G06F2212/69 ,  G06F2212/70

Abstract: A method of maintaining a device table cache (DTC) included in a Synchronous input/output (I/O) computing system includes issuing, with a processor executing an operating system running on the Synchronous I/O computing system, a Synchronous I/O command indicating a request to perform a device table entry transaction including a plurality of device table entries. The method also includes determining, with a host bridge processor, based on device table information, whether the device table entry transaction is associated with a cyclic redundancy check (CRC) transaction, and pinning, with the host bridge processor, a device table entry from a device table based on the determination.

公开(公告)号：US09870322B2

公开(公告)日：2018-01-16

申请号：US14939063

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Matthias Klein ,  Marco Kraemer ,  Carsten Otte ,  Christoph Raisch

IPC: G06F12/10 ,  G06F9/50 ,  G06F12/02 ,  G06F12/1027 ,  G06F12/109 ,  G06F12/1009

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/5077 ,  G06F12/023 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/109 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/656 ,  G06F2212/68 ,  G06F2212/684

Abstract: In an approach for determining a physical address for object access in an object-based storage device (OSD) system, a processor divides a first data object into one or more partitions, including at least a first partition, and providing each partition for storage as individual stored objects in an OSD system. A processor adds a first entry in a page table, the first entry representing the first partition without an indication of a physical address. A memory management unit (MMU) of the OSD system receives a first request of the first partition. Responsive to receiving the first request of the first partition, a MMU identifies that the first entry of the page table represents the first partition. A MMU obtains a physical address of the first partition from one of a hardware component and a firmware component.