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    Three-dimensional memory array
    121.
    发明授权
    Three-dimensional memory array 有权

    公开(公告)号：US10593730B1

    公开(公告)日：2020-03-17

    申请号：US16156194

    申请日：2018-10-10

    Applicant: Micron Technology, Inc.

    Inventor： Anna Maria Conti ,  Andrea Redaelli ,  Agostino Pirovano

    IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.

    TECHNIQUES FOR PROGRAMMING A MEMORY CELL
    122.
    发明申请
    TECHNIQUES FOR PROGRAMMING A MEMORY CELL 审中-公开

    公开(公告)号：US20200066343A1

    公开(公告)日：2020-02-27

    申请号：US16108784

    申请日：2018-08-22

    Applicant: Micron Technology, Inc.

    Inventor： Hernan A. Castro ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer

    IPC: G11C13/00 ,  G11C5/06

    Abstract: Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be reduced (e.g., during a selection time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may result in the memory cell storing a second logic state different than the first logic state.

    TAPERED MEMORY CELL PROFILES
    123.
    发明申请
    TAPERED MEMORY CELL PROFILES 审中-公开

    公开(公告)号：US20200020855A1

    公开(公告)日：2020-01-16

    申请号：US16534937

    申请日：2019-08-07

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Kolya Yastrebenetsky ,  Fabio Pellizzer

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    Abstract: Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode.

    TAPERED MEMORY CELL PROFILES
    124.
    发明申请
    TAPERED MEMORY CELL PROFILES 审中-公开

    公开(公告)号：US20190252607A1

    公开(公告)日：2019-08-15

    申请号：US15893106

    申请日：2018-02-09

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Kolya Yastrebenetsky ,  Fabio Pellizzer

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    CPC classification number: H01L45/1273 ,  G11C13/0004 ,  G11C13/004 ,  G11C2213/52 ,  G11C2213/71 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/141

    Abstract: Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode.

    MULTI-LEVEL SELF-SELECTING MEMORY DEVICE
    125.
    发明申请
    MULTI-LEVEL SELF-SELECTING MEMORY DEVICE 审中-公开

    公开(公告)号：US20190189203A1

    公开(公告)日：2019-06-20

    申请号：US15842496

    申请日：2017-12-14

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer

    IPC: G11C11/56 ,  G11C13/00 ,  H01L45/00

    Abstract: Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

    THREE DIMENSIONAL MEMORY ARRAYS
    127.
    发明申请
    THREE DIMENSIONAL MEMORY ARRAYS 审中-公开

    公开(公告)号：US20190088714A1

    公开(公告)日：2019-03-21

    申请号：US15710972

    申请日：2017-09-21

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Russell L. Meyer ,  Agostino Pirovano ,  Lorenzo Fratin

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.

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