公开(公告)号：US11538822B2

公开(公告)日：2022-12-27

申请号：US16445065

申请日：2019-06-18

Applicant: Micron Technology, inc.

Inventor： John D. Hopkins ,  Justin D. Shepherdson ,  Collin Howder ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/02 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/285 ,  H01L27/11519 ,  H01L29/66 ,  H01L21/28

Abstract: Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.

公开(公告)号：US11515320B2

公开(公告)日：2022-11-29

申请号：US17012741

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Nancy M. Lomeli

IPC: H01L27/11575 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/538 ,  G11C5/06 ,  G11C5/02

Abstract: A method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US11482534B2

公开(公告)日：2022-10-25

申请号：US16861093

申请日：2020-04-28

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Meng-Wei Kuo ,  John D. Hopkins

IPC: H01L21/8239 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/1157

Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.

公开(公告)号：US11411012B2

公开(公告)日：2022-08-09

申请号：US15930724

申请日：2020-05-13

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins

IPC: H01L21/20 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack, that will comprise vertically-alternating first tiers and second tiers, on a substrate. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines are formed in a lowest first tier and that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material of different composition from the first-tier material that is or will be formed above the lowest first tier and from the second-tier material that is or will be formed above the lowest first tier. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines. Channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend to the line there-between. The sacrificial material of the lines is removed through the trenches. Intervening material is formed in the trenches and void-spaces left as a result of the removing of the sacrificial material of the lines. Other embodiments are disclosed.

公开(公告)号：US20220231042A1

公开(公告)日：2022-07-21

申请号：US17150322

申请日：2021-01-15

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli

IPC: H01L27/11582 ,  H01L21/225 ,  H01L27/11556

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming vertically-extending channel-material strings into a stack comprising vertically-alternating first tiers and second tiers. Material of the first tiers is of different composition from material of the second tiers. A liner is formed laterally-outside of individual of the channel-material strings in one of the first tiers and in one of the second tiers. The liners are isotropically etched to form void-spaces in the one second tier above the one first tier. Individual of the void-spaces are laterally-between the individual channel-material strings and the second-tier material in the one second tier. Conductively-doped semiconductive material is formed against sidewalls of the channel material of the channel-material strings in the one first tier and that extends upwardly into the void-spaces in the one second tier. The conductively-doped semiconductive material is heated to diffuse conductivity-increasing dopants therein from the void-spaces laterally into the channel material laterally there-adjacent and upwardly into the channel material that is above the void-spaces. Other aspects, including structure independent of method, are disclosed.

公开(公告)号：US11387243B2

公开(公告)日：2022-07-12

申请号：US15931299

申请日：2020-05-13

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material-string structures of memory cells extend through the insulative tiers and the conductive tiers. The channel-material-string structures individually comprise an upper portion above and joined with a lower portion. Individual of the channel-material-string structures comprise at least one external jog surface in a vertical cross-section where the upper and lower portions join. Other embodiments, including method are disclosed.

公开(公告)号：US20220216229A1

公开(公告)日：2022-07-07

申请号：US17141968

申请日：2021-01-05

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  John D. Hopkins ,  Matthew J. King ,  Roger W. Lindsay ,  Kevin Y. Titus

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556

Abstract: A microelectronic device includes a pair of stack structures. The pair comprises a lower stack structure and an upper stack structure overlying the lower stack structure. The lower stack structure and the upper stack structure each comprise a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A source region is vertically interposed between the lower stack structure and the upper stack structure. A first array of pillars extends through the upper stack structure, from proximate the source region toward a first drain region above the upper stack structure. A second array of pillars extend through the lower stack structure, from proximate the source region toward a second drain region below the lower stack structure. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.

公开(公告)号：US20220216094A1

公开(公告)日：2022-07-07

申请号：US17141722

申请日：2021-01-05

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  John D. Hopkins ,  Madison D. Drake

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, strings of memory cells vertically extending through the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, a conductive contact structure vertically overlying and in electrical communication with the channel material of a string of memory cells of the strings of memory cells, and a void laterally neighboring the conductive contact structure, the conductive contact structure separated from a laterally neighboring conductive contact structure by the void, a dielectric material, and an additional void laterally neighboring the laterally neighboring conductive contact structure. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US11315877B2

公开(公告)日：2022-04-26

申请号：US16817267

申请日：2020-03-12

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Rita J. Klein ,  Everett A. McTeer ,  Lifang Xu ,  Daniel Billingsley ,  Collin Howder

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US11302710B2

公开(公告)日：2022-04-12

申请号：US16739332

申请日：2020-01-10

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Matthew J. King ,  John D. Hopkins ,  M. Jared Barclay

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11573 ,  H01L23/48

Abstract: Some embodiments include an integrated assembly having a base (e.g., a monocrystalline silicon wafer), and having memory cells over the base and along channel-material-pillars. A conductive structure is between the memory cells and the base. The channel-material-pillars are coupled with the conductive structure. A foundational structure extends into the base and projects upwardly to a level above the conductive structure. The foundational structure locks the conductive structure to the base to provide foundational support to the conductive structure.