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    Staircase formation in a memory array
    1.
    发明授权
    Staircase formation in a memory array 有权

    公开(公告)号：US12245426B2

    公开(公告)日：2025-03-04

    申请号：US17822712

    申请日：2022-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  Lifang Xu ,  Jordan D. Greenlee

    IPC: H10B43/20 ,  G11C16/08 ,  H01L21/768 ,  H10B43/35

    Abstract: Methods, systems, and devices for staircase formation in a memory array are described. A first liner material may be deposited on a tread above a first contact surface and a portion of the first liner material may be doped. A second liner material may be deposited over the first liner and a portion of the second liner material may be doped. After doping the portions of the liner materials, the undoped portions of the liner materials may be removed so that the materials above a second contact surface can be at least partially removed via a first removal process. The doped portion of the first liner material may then be cut back so that a second removal process can expose the second contact surface and a third contact (while the first contact surface is protected from the removal process by the liner materials).

    Array Of Capacitors, Array Of Memory Cells, And Methods Used In Forming An Array Of Capacitors
    3.
    发明公开
    Array Of Capacitors, Array Of Memory Cells, And Methods Used In Forming An Array Of Capacitors 审中-公开

    公开(公告)号：US20240237330A1

    公开(公告)日：2024-07-11

    申请号：US18407675

    申请日：2024-01-09

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  Andrea Gotti ,  David McShannon ,  Silvia Borsari

    IPC: H10B12/00 ,  G11C5/06

    CPC classification number: H10B12/31 ,  G11C5/063 ,  H01L28/91 ,  H10B12/482 ,  H10B12/488

    Abstract: A method used in forming an array of capacitors comprises forming horizontally-spaced openings into sacrificial material and through insulative material that is between a top and bottom of the sacrificial material. The insulative material at least predominately comprises at least one of a silicon nitride, a silicon boronitride, and a silicon carbonitride. The insulative material with horizontally-spaced openings there-through comprises an insulative horizontal lattice. An insulative lining is deposited within the horizontally-spaced openings and directly above the sacrificial material. The insulative lining at least predominately comprises at least one of a silicon oxide and a silicon oxynitride. During the depositing, the insulative lining is intermittently exposed to a nitrogen-containing plasma. First capacitor electrodes that are individually within individual of the horizontally-spaced openings are formed laterally over the insulative lining that is in the horizontally-spaced openings. The sacrificial material is removed and a capacitor insulator is formed over the first capacitor electrodes and the insulative horizontal lattice. Second-capacitor-electrode material is formed over the capacitor insulator. Structure independent of method is disclosed.

    Memory Circuitry And Methods Used In Forming Memory Circuitry
    4.
    发明公开
    Memory Circuitry And Methods Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20240172412A1

    公开(公告)日：2024-05-23

    申请号：US18241035

    申请日：2023-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Li Wei Fang ,  Vivek Yadav ,  Jordan D. Greenlee ,  Silvia Borsari

    IPC: H10B12/00

    CPC classification number: H10B12/053 ,  H10B12/315 ,  H10B12/34

    Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Openings are formed through insulative material that is directly above the transistors and into the another source/drain regions. Individual of the openings are directly above individual of the another source/drain regions. A laterally-outer insulator material is formed in the individual openings within and below the insulative material. A laterally-inner insulator material is formed in the individual openings within and below the insulative material laterally-over the laterally-outer insulator material. The laterally-outer insulator material and the laterally-inner insulator material are directly against one another and have an interface there-between. The laterally-inner insulator material that is in the individual openings below the insulative material is removed. After such removing, conductor material is formed in the individual openings that is electrically coupled to one of the individual another source/drain regions. The laterally-outer insulator material, the laterally-inner insulator material, and the conductor material that are in the individual openings comprise individual conductive-via constructions. Digitlines are formed directly above the insulative material and that are individually electrically coupled to the conductor material of one of the individual conductive-via constructions. Storage elements are formed that are individually electrically coupled to individual of the one source/drain regions. Structure is disclosed.

    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    7.
    发明公开
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 审中-公开

    公开(公告)号：US20230397420A1

    公开(公告)日：2023-12-07

    申请号：US17830108

    申请日：2022-06-01

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Nancy M. Lomeli ,  Jordan D. Greenlee

    IPC: H01L27/11582 ,  H01L27/11556

    CPC classification number: H01L27/11582 ,  H01L27/11556

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings extend through the first tiers and the second tier. Conducting material is formed in a lower of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The forming of the conducting material comprises forming conductive material in the lower first tier against the channel material of the individual channel-material strings. The conductive material comprises an upper portion and a lower portion having a void-space vertically there-between. The void-space comprises an exposed silicon-containing surface. Silicon is selectively deposited into the void-space onto and from the exposed silicon-containing surface. Other embodiments, including structure independent of method, are disclosed.

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