公开(公告)号：US20210143842A1

公开(公告)日：2021-05-13

申请号：US17157141

申请日：2021-01-25

Applicant: Micron Technology, Inc.

Inventor： Patrick R. Khayat ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak

IPC: H03M13/29

Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.

公开(公告)号：US10693504B2

公开(公告)日：2020-06-23

申请号：US16162278

申请日：2018-10-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Patrick R. Khayat ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak

IPC: H03M13/29 ,  G06F11/10 ,  H03M13/15 ,  G11C29/52

Abstract: An apparatus is provided. The apparatus comprises a first syndrome computation circuit configured to receive a codeword having a plurality of rows and a plurality of columns and further configured to compute a first syndrome for at least a portion of a first component codeword of the codeword. The apparatus further comprises a second syndrome computation circuit configured to receive the codeword and to compute a second syndrome for at least a portion of a second component codeword of the codeword. The apparatus further comprises a bit correction circuit configured to correct one or more erroneous bits in the codeword based, at least in part, on at least one of the first and second syndrome, wherein the first and second component codewords span two or more rows and two or more columns of the codeword.

公开(公告)号：US20190310912A1

公开(公告)日：2019-10-10

申请号：US15950137

申请日：2018-04-10

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Nicholas J. Richardson ,  Patrick R. Khayat ,  Shantilal Doru

IPC: G06F11/10 ,  H03M13/29

Abstract: A product code decoder to implement a method of bit correction in a codeword buffer to support error correcting code (ECC). The method loads a location entry from a correction queue, where the location entry includes a data word address and bit location information. The method performs a fast path data word address comparison to determine whether data from the data word address is being processed by a previous entry from the correction queue. The method further combines a correction of the data at the data word address specified by the location entry with a correction of a copy of the data being processed based on a previous location entry, in response to a fast path data word address comparison match, and stores the combined data in the codeword buffer.

公开(公告)号：US10340014B2

公开(公告)日：2019-07-02

申请号：US15873024

申请日：2018-01-17

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Patrick R. Khayat ,  Sivagnanam Parthasarathy

IPC: G11C29/00 ,  G11C16/26 ,  G11C29/52 ,  H03M13/45 ,  G06F11/10 ,  G11C29/02 ,  H03M13/11 ,  H03M13/13 ,  H03M13/37 ,  G11C16/04 ,  G11C29/04

Abstract: The present disclosure includes apparatuses and methods for monitoring error correction operations performed in memory. A number of embodiments include a memory and circuitry configured to determine a quantity of erroneous data corrected during an error correction operation performed on soft data associated with a sensed data state of a number of memory cells of the memory, determine a quality of soft information associated with the erroneous data corrected during the error correction operation performed on the soft data, and determine whether to take a corrective action on the sensed data based on the quantity of the erroneous data corrected during the error correction operation and the quality of the soft information associated with the erroneous data corrected during the error correction operation.

公开(公告)号：US10326479B2

公开(公告)日：2019-06-18

申请号：US15206799

申请日：2016-07-11

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Patrick R. Khayat ,  Sivagnanam Parthasarathy ,  Nicholas J. Richardson

IPC: H03M13/45 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  H03M13/29 ,  H03M13/37 ,  G11C29/04 ,  H03M13/15

Abstract: One example of layer-by-layer error correction can include iteratively error correcting the codeword on a layer-by-layer basis with the first error correction circuit in a first mode and determining on the layer-by-layer basis whether a number of parity errors in a particular layer is less than a threshold number of parity errors. The codeword can be transferred to a second error correction circuit when the number of parity errors is less than the threshold number of parity errors. The codeword can be iteratively error corrected with the first error correction circuit in a second mode when the number of parity errors is at least the threshold number of parity errors. The threshold number of parity errors can be at least partially based on an adjustable code rate of the first error correction circuit or the second error correction circuit.

公开(公告)号：US10312944B2

公开(公告)日：2019-06-04

申请号：US15461623

申请日：2017-03-17

Applicant: Micron Technology, Inc.

Inventor： Patrick R. Khayat ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak

IPC: H03M13/00 ,  H03M13/29 ,  H03M13/15

Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.

公开(公告)号：US20190149175A1

公开(公告)日：2019-05-16

申请号：US16244627

申请日：2019-01-10

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  William H. Radke ,  Patrick R. Khayat ,  Sivagnanam Parthasarathy

IPC: H03M13/37 ,  G11C29/52 ,  G06F11/10 ,  H03M13/29 ,  H03M13/11

Abstract: The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer.

公开(公告)号：US20190058493A1

公开(公告)日：2019-02-21

申请号：US16162278

申请日：2018-10-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Patrick R. Khayat ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak

IPC: H03M13/29 ,  G06F11/10 ,  H03M13/15 ,  G11C29/52

Abstract: An apparatus is provided. The apparatus comprises a first syndrome computation circuit configured to receive a codeword having a plurality of rows and a plurality of columns and further configured to compute a first syndrome for at least a portion of a first component codeword of the codeword. The apparatus further comprises a second syndrome computation circuit configured to receive the codeword and to compute a second syndrome for at least a portion of a second component codeword of the codeword. The apparatus further comprises a bit correction circuit configured to correct one or more erroneous bits in the codeword based, at least in part, on at least one of the first and second syndrome, wherein the first and second component codewords span two or more rows and two or more columns of the codeword.

公开(公告)号：US20180341546A1

公开(公告)日：2018-11-29

申请号：US16055384

申请日：2018-08-06

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Patrick R. Khayat ,  Nicholas J. Richardson

IPC: G06F11/10 ,  H03M13/00 ,  G06F11/07 ,  H03M13/37 ,  H03M13/11 ,  G11C29/56 ,  G11C29/52 ,  G11C29/00 ,  G11C11/56 ,  G06F11/08 ,  G11C29/04

CPC classification number: G06F11/1048 ,  G06F11/07 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/08 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5642 ,  G11C29/00 ,  G11C29/52 ,  G11C29/56008 ,  G11C2029/0411 ,  H03M13/1102 ,  H03M13/3715 ,  H03M13/3738 ,  H03M13/612

Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.

公开(公告)号：US10110256B2

公开(公告)日：2018-10-23

申请号：US15267967

申请日：2016-09-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Patrick R. Khayat ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak

IPC: H03M13/29 ,  G06F11/10 ,  G11C29/52 ,  H03M13/15

Abstract: An apparatus is provided. The apparatus comprises a first syndrome computation circuit configured to receive a codeword having a plurality of rows and a plurality of columns and further configured to compute a first syndrome for at least a portion of a first component codeword of the codeword. The apparatus further comprises a second syndrome computation circuit configured to receive the codeword and to compute a second syndrome for at least a portion of a second component codeword of the codeword. The apparatus further comprises a bit correction circuit configured to correct one or more erroneous bits in the codeword based, at least in part, on at least one of the first and second syndrome, wherein the first and second component codewords span two or more rows and two or more columns of the codeword.