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    Communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures, circuits, and data apparatuses
    121.
    发明授权
    Communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures, circuits, and data apparatuses 有权
    通信方法，形成互连的方法，信号互连，集成电路结构，电路和数据装置

    公开(公告)号：US09046649B2

    公开(公告)日：2015-06-02

    申请号：US13898356

    申请日：2013-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Chandra Mouli

    IPC: G02B6/00 ,  G02B6/13 ,  G02B6/122 ,  G02B6/132 ,  G02B6/43 ,  G02B6/12

    CPC classification number: G02B6/13 ,  G02B6/1226 ,  G02B6/132 ,  G02B6/43 ,  G02B2006/12176

    Abstract: Some embodiments include communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures, circuits, and data apparatuses. In one embodiment, a communication method includes accessing an optical signal comprising photons to communicate information, accessing an electrical signal comprising electrical data carriers to communicate information, and using a single interconnect, communicating the optical and electrical signals between a first spatial location and a second spatial location spaced from the first spatial location.

    Abstract translation: 一些实施例包括通信方法，形成互连的方法，信号互连，集成电路结构，电路和数据装置。 在一个实施例中，通信方法包括访问包括光子的光信号以传达信息，访问包括电数据载体的电信号以传送信息，以及使用单个互连，在第一空间位置和第二空间位置之间传送光信号和电信号 与第一空间位置间隔开的空间位置。

    Transistors comprising a SiC-containing channel
    124.
    发明授权
    Transistors comprising a SiC-containing channel 有权
    晶体管包括含SiC通道

    公开(公告)号：US08703566B2

    公开(公告)日：2014-04-22

    申请号：US13901719

    申请日：2013-05-24

    Applicant: Micron Technology, Inc.

    Inventor： Chandra Mouli

    IPC: H01L21/336

    CPC classification number: H01L29/66666 ,  H01L21/8213 ,  H01L27/105 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10879 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/785 ,  Y10S438/931

    Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.

    Abstract translation: 存储器件包括存储器单元阵列和外围设备。 至少一些单独的记忆单元包括含有SiC的碳酸化部分。 至少一些外围设备不包括任何碳酸化部分。 晶体管包括第一源极/漏极，第二源极/漏极，包括在第一和第二源极/漏极之间包含SiC的半导体衬底的碳酸化部分的沟道以及与沟道的相对侧可操作地相关联的栅极。

    Floating Body Field-Effect Transistors, and Methods of Forming Floating Body Field-Effect Transistors
    125.
    发明申请
    Floating Body Field-Effect Transistors, and Methods of Forming Floating Body Field-Effect Transistors 有权
    浮体场效应晶体管，以及形成浮体场效应晶体管的方法

    公开(公告)号：US20140051214A1

    公开(公告)日：2014-02-20

    申请号：US13761587

    申请日：2013-02-07

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch ,  Di Li

    IPC: H01L27/12 ,  H01L27/108 ,  H01L29/66

    CPC classification number: H01L27/1203 ,  H01L27/10802 ,  H01L29/66477 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

    Abstract translation: 在一个实施例中，浮体场效应晶体管包括一对在其间容纳浮体通道区的源/漏区。 源极/漏极区域和浮体沟道区域被接纳在绝缘体上。 栅电极靠近浮体通道区域。 门电介质被接收在栅电极和浮体沟道区之间。 浮体通道区域具有半导体SixGe（1-x）区域。 浮体通道区域具有容纳在半导体SixGe（1-x）区域和栅极电介质之间的半导体硅包覆区域。 半导体SixGe（1-x）含量区域在含半导体硅的区域内具有比任何Ge量更大的Ge量。 考虑了其他实施例，包括形成浮体场效应晶体管的方法。

    JFET DEVICE STRUCTURES AND METHODS FOR FABRICATING THE SAME
    126.
    发明申请
    JFET DEVICE STRUCTURES AND METHODS FOR FABRICATING THE SAME 有权
    JFET器件结构及其制造方法

    公开(公告)号：US20130285124A1

    公开(公告)日：2013-10-31

    申请号：US13925471

    申请日：2013-06-24

    Applicant: Micron Technology, Inc.

    Inventor： Chandra Mouli

    IPC: H01L29/808 ,  H01L27/098

    CPC classification number: H01L27/098 ,  H01L21/22 ,  H01L21/225 ,  H01L21/2251 ,  H01L21/3226 ,  H01L21/385 ,  H01L27/108 ,  H01L27/1203 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/80 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/8086

    Abstract: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.

    Abstract translation: 根据本技术，提供了一种JFET器件结构及其制造方法。 具体地，提供了包括具有源极和漏极的半导体衬底的晶体管。 晶体管还包括形成在源极和漏极之间的半导体衬底中的掺杂沟道，该沟道被配置为在源极和漏极之间传导电流。 此外，晶体管具有包括在沟道上形成的半导体材料的栅极和栅极每侧上的电介质间隔物。 源极和漏极在空间上与栅极分离，使得栅极不在漏极和源极之上。

    Communication Methods, Methods of Forming an Interconnect, Signal Interconnects, Integrated Circuit Structures, Circuits, and Data Apparatuses
    127.
    发明申请
    Communication Methods, Methods of Forming an Interconnect, Signal Interconnects, Integrated Circuit Structures, Circuits, and Data Apparatuses 有权
    通信方法，形成互连的方法，信号互连，集成电路结构，电路和数据设备

    公开(公告)号：US20130252359A1

    公开(公告)日：2013-09-26

    申请号：US13898356

    申请日：2013-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Chandra Mouli

    IPC: G02B6/13

    CPC classification number: G02B6/13 ,  G02B6/1226 ,  G02B6/132 ,  G02B6/43 ,  G02B2006/12176

    Abstract: Some embodiments include communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures, circuits, and data apparatuses. In one embodiment, a communication method includes accessing an optical signal comprising photons to communicate information, accessing an electrical signal comprising electrical data carriers to communicate information, and using a single interconnect, communicating the optical and electrical signals between a first spatial location and a second spatial location spaced from the first spatial location.

    Abstract translation: 一些实施例包括通信方法，形成互连的方法，信号互连，集成电路结构，电路和数据装置。 在一个实施例中，通信方法包括访问包括光子的光信号以传达信息，访问包括电数据载体的电信号以传送信息，以及使用单个互连，在第一空间位置和第二空间位置之间传送光信号和电信号 与第一空间位置间隔开的空间位置。

    Memory cell comprising a floating body, a channel region, and a diode
    128.
    发明授权
    Memory cell comprising a floating body, a channel region, and a diode 有权
    存储单元包括浮体，沟道区和二极管

    公开(公告)号：US08525248B2

    公开(公告)日：2013-09-03

    申请号：US13717465

    申请日：2012-12-17

    Applicant: Micron Technology, Inc.

    Inventor： Chandra Mouli

    IPC: H01L29/788

    CPC classification number: H01L29/7841 ,  H01L27/1021 ,  H01L27/10802 ,  H01L29/1608

    Abstract: Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type as the floating bodies, and such sections of the gated diodes may be electrically connected to the floating bodies. The floating bodies may be adjacent channel regions, and spaced from the channel regions by a dielectric structure. The dielectric structure of a memory cell may have a first portion between the floating body and the diode, and may have a second portion between the floating body and the channel region. The first portion may be more leaky to charge carriers than the second portion. The diodes may be formed in semiconductor material that is different from a semiconductor material that the channel regions are in. The floating bodies may have bulbous lower regions. Some embodiments include methods of making memory cells.

    Abstract translation: 一些实施例包括含有浮体和二极管的存储单元。 二极管可以是具有掺杂到与浮体相同的导电类型的部分的门极二极管，并且门控二极管的这些部分可以电连接到浮体。 浮体可以是相邻的沟道区，并且通过电介质结构与沟道区隔开。 存储单元的电介质结构可以具有在浮体和二极管之间的第一部分，并且可以在浮体和沟道区之间具有第二部分。 与第二部分相比，第一部分对于载流子的泄漏可能更多。 二极管可以形成为不同于沟道区域的半导体材料的半导体材料。浮体可以具有球形的下部区域。 一些实施例包括制造存储器单元的方法。

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