公开(公告)号：US07227782B2

公开(公告)日：2007-06-05

申请号：US11285273

申请日：2005-11-22

申请人： Seung-Jae Lee ,  Jung-Hoon Park

发明人： Seung-Jae Lee ,  Jung-Hoon Park

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C29/846

摘要： A NAND flash memory device which includes a first page buffer circuit reading main data bits from the main field during a read operation, a second page buffer circuit reading redundant data bits from the redundancy field during the read operation, a first column gate circuit configured to select a part of the read main data bits and a part of the read redundant data bits in response to first column selection signals at the same time, and a second column gate circuit configured to select a part of the selected main data bits in response to second column selection signals.

摘要翻译： 一种NAND闪速存储器件，包括在读取操作期间从主场读取主要数据位的第一页缓冲器电路，在读取操作期间从冗余场读取冗余数据位的第二页缓冲器电路，配置为 响应于第一列选择信号同时选择读取的主数据位的一部分和读取的冗余数据位的一部分，以及第二列门电路，被配置为响应于所选择的主数据位选择一部分 第二列选择信号。

公开(公告)号：US07176747B2

公开(公告)日：2007-02-13

申请号：US10940808

申请日：2004-08-24

申请人： Seung-Jae Lee ,  Dae-Seok Byeon

发明人： Seung-Jae Lee ,  Dae-Seok Byeon

IPC分类号： G05F1/10

CPC分类号： G11C16/30 ,  G11C5/145 ,  H02M3/07 ,  H02M2001/009 ,  H03H11/245

摘要： A multi-level high voltage generator according to embodiments of the invention is capable of simultaneously generating high voltages of various levels by using one charge pump. The multi-level high voltage generator includes a charge pump unit, a voltage divider unit, and a pump control unit. The charge pump unit raises an input voltage applied at an input terminal to simultaneously output a number of high voltages having different levels. The voltage divider unit divides the voltages from the charge pump unit. The pump control unit operates according to an enable signal and generates pump control signals in response to a reference voltage, a control clock signal, and a divided voltage from the voltage divider unit. The charge pump unit generates the high voltages and is controlled by the pump control signals from the pump control unit.

摘要翻译： 根据本发明的实施例的多电平高压发生器能够通过使用一个电荷泵同时产生各种电平的高电压。 多电平高压发生器包括电荷泵单元，分压器单元和泵控制单元。 电荷泵单元提高施加在输入端子处的输入电压，以同时输出具有不同电平的多个高电压。 分压器单元分离电荷泵单元的电压。 泵控制单元根据使能信号进行工作，响应于参考电压，控制时钟信号和来自分压器单元的分压产生泵控制信号。 电荷泵单元产生高电压并由来自泵控制单元的泵控制信号控制。

公开(公告)号：US20060219702A1

公开(公告)日：2006-10-05

申请号：US11281706

申请日：2005-11-18

申请人： Seung-Jae Lee

发明人： Seung-Jae Lee

IPC分类号： H05B1/02

CPC分类号： H05K5/0017 ,  B41J3/46

摘要： An electronic appliance is provided including a display unit movably installed along a guide rail, a protection cover which slides between a first position covering the display unit and a second position exposing the display unit, and a connection unit connecting the sliding movement of the protection cover between the first and second positions with the movement of the display unit.

摘要翻译： 一种电子设备，包括：沿着导轨可移动地安装的显示单元，在覆盖显示单元的第一位置和暴露显示单元的第二位置之间滑动的保护盖;以及连接单元，其将保护盖的滑动运动 在显示单元的移动之间的第一和第二位置之间。

公开(公告)号：US06988042B2

公开(公告)日：2006-01-17

申请号：US10722089

申请日：2003-11-25

申请人： Myoen-Song Choi ,  Seung-Jae Lee

发明人： Myoen-Song Choi ,  Seung-Jae Lee

IPC分类号： G01R31/00 ,  G01R31/14

CPC分类号： H02H1/0092 ,  G01R31/088 ,  H02H3/40

摘要： The present invention relates to a method for detecting a line-to-line fault location in power network, and more particularly, detecting the line-to-line fault location by direct 3-phase circuit analysis without using a symmetrical component transformation, so even in an unbalanced 3-phase circuit, the line-to-line fault location can be accurately detected. In the method using direct 3-phase circuit analysis of this invention, inverse lemma is used to simplify matrix inversion calculations, thus the line-to-line fault location can be easily and accurately determined even in the case of an unbalanced network without symmetrical component transformation.

摘要翻译： 本发明涉及一种用于检测电力线路中线路故障定位的方法，更具体地，涉及通过直接三相电路分析检测线间故障定位而不使用对称分量变换， 在不平衡的三相电路中，可以准确地检测到线路故障位置。 在使用本发明的直接三相电路分析的方法中，使用逆引理来简化矩阵反演计算，因此即使在不对称分量的不平衡网络的情况下也可以容易且准确地确定线对线故障位置 转型。

公开(公告)号：US20050110205A1

公开(公告)日：2005-05-26

申请号：US10970652

申请日：2004-10-22

申请人： Seung-Jae Lee ,  Sang-Jin Bae

发明人： Seung-Jae Lee ,  Sang-Jin Bae

IPC分类号： B65H5/00 ,  B65H5/22 ,  G03G15/00 ,  H04N1/00 ,  H04N1/31

CPC分类号： G03G15/602 ,  G03G2215/00189

摘要： An automatic document feeder for an image forming apparatus comprising a separation roller for separately carrying a plurality of paper sheets picked by a pickup roller, a feeding roller for carrying the paper sheets, a discharge roller for discharging the scanned paper sheets, and a transmission unit for transmitting a driving force from a driving motor. The transmission unit comprises an internal roller installed on the same axis as the feeding roller, the internal roller having an internal gear, a swing arm rotatably attached to a bracket, the bracket being inserted into the internal roller, and a swing gear rotatably installed on one side of the swing arm, the swing gear being engaged with the internal gear for rotating the internal roller.

摘要翻译： 一种用于图像形成装置的自动送稿器，包括分离辊，用于分别承载由拾取辊拾取的多个纸张，用于承载纸张的进给辊，用于排出扫描纸张的排出辊以及传送单元 用于从驱动电机传递驱动力。 传动单元包括安装在与进给辊相同的轴线上的内部辊，内部辊具有内部齿轮，可旋转地附接到支架的摆臂，插入内部辊的支架和可旋转地安装在 摆臂的一侧，摆动齿轮与内齿轮啮合，用于旋转内辊。

公开(公告)号：US06678191B2

公开(公告)日：2004-01-13

申请号：US10165838

申请日：2002-06-06

申请人： Seung-Jae Lee ,  Young-Ho Lim

发明人： Seung-Jae Lee ,  Young-Ho Lim

IPC分类号： G11C1604

CPC分类号： G11C7/106 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/18 ,  G11C11/005 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/002

摘要： Disclosed is a nonvolatile semiconductor memory device having a memory cell array by which random access can be performed. The memory cell array structure of the nonvolatile semiconductor memory device having a main memory cell array formed of a plurality of NAND cell strings includes a sub memory cell array having a plurality of NAND cell strings that is provided therein with memory cell transistors. The number of the memory cell transistors in the sub memory cell array is less than that of the memory cell transistors in the NAND cell strings of the main memory cell arrays. The sub memory cell array is operationally connected to main bit lines of the main memory cell array during program and erase operations and is electrically disconnected with the main bit lines during read operation, thereby having a separate read path that is independent from the read path of the main memory cell array.

摘要翻译： 公开了一种具有可以进行随机存取的存储单元阵列的非易失性半导体存储器件。 具有由多个NAND单元串构成的主存储单元阵列的非易失性半导体存储器件的存储单元阵列结构包括具有在其中设置有存储单元晶体管的多个NAND单元串的副存储单元阵列。 子存储单元阵列中的存储单元晶体管的数量小于主存储单元阵列的NAND单元串中的存储单元晶体管的数量。 子存储单元阵列在编程和擦除操作期间可操作地连接到主存储单元阵列的主位线，并且在读取操作期间与主位线电连接，从而具有独立于读取路径的读取路径 主存储单元阵列。

公开(公告)号：US06448149B1

公开(公告)日：2002-09-10

申请号：US09608030

申请日：2000-06-30

申请人： Seung-Jae Lee ,  Soo-Seun Lee ,  Hoon Lim

发明人： Seung-Jae Lee ,  Soo-Seun Lee ,  Hoon Lim

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： A method for making the Shallow Trench Isolation (STI) of a semiconductor device. An active mask layer is formed on a semiconductor substrate. Then the active mask layer and semiconductor substrate are etched to form a plurality of trenches. Next, an oxide layer is deposited by High Density Plasma Chemical Vapor Deposition (HDP-CVD) over the active mask layer so as to fill the trenches to a thickness greater than the depth of the trenches and less than the sum of the depth and the thickness of the active mask layer. A capping oxide layer is formed over the HDP-CVD oxide layer by means of plasma source of Tetra-Ethyl-Ortho-Silicate (TEOS). Subsequently, the capping oxide layer and HDP-CVD oxide layer are polished so as to expose the active mask layer. Thus, the Idoff characteristics of the transistor and thus the refresh characteristics of DRAM can be improved. Further, in another embodiment of the present invention, the HDP-CVD oxide layer partially fills the trenches, reducing the aspect ratio of the trenches. As a result, subsequent ozone-TEOS USG layer can completely fill the trenches without the formation of voids.

摘要翻译： 制造半导体器件的浅沟槽隔离（STI）的方法。 在半导体衬底上形成有源掩模层。 然后蚀刻有源掩模层和半导体衬底以形成多个沟槽。 接下来，在有源掩模层上通过高密度等离子体化学气相沉积（HDP-CVD）沉积氧化物层，以便将沟槽填充到大于沟槽深度的厚度，并且小于深度和 活性掩模层的厚度。 通过四乙基 - 正硅酸盐（TEOS）的等离子体源在HDP-CVD氧化物层上形成覆盖氧化物层。 随后，对封盖氧化物层和HDP-CVD氧化物层进行抛光，以露出活性掩模层。 因此，可以提高晶体管的Idoff特性和DRAM的刷新特性。 此外，在本发明的另一个实施例中，HDP-CVD氧化物层部分地填充沟槽，减小了沟槽的纵横比。 结果，随后的臭氧TEOS USG层可以完全填充沟槽而不形成空隙。

公开(公告)号：US06372555B1

公开(公告)日：2002-04-16

申请号：US09399926

申请日：1999-09-21

申请人： Seung-Jae Lee ,  Tae-Wook Seo ,  Sun-Hoo Park

发明人： Seung-Jae Lee ,  Tae-Wook Seo ,  Sun-Hoo Park

IPC分类号： H01L2182

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A novel fuse structure for a semiconductor integrated circuit device and the method of manufacturing the semiconductor integrated circuit device is disclosed. The fuse structure is comprised of a first interconnection metal layer formed on a semiconductor substrate; an inter-metal dielectric layer formed on the first interconnection metal layer having a via exposing the first interconnection metal layer; a via plug filling up the via; a metal layer for a fuse and a second interconnection metal layer consecutively deposited on the via plug and the inter-metal dielectric layer; and an opening area exposing the metal layer for a fuse is positioned more than twice the thickness of the second interconnection metal layer from the via. With the present invention, a contact failure which can result from a damage to via plug in a subsequent stripping step can be prevented. Also, a passivation layer formed after opening the fuse area prevents a short-circuit between adjacent fuses in a subsequent laser repairing process.

摘要翻译： 公开了一种用于半导体集成电路器件的新型熔丝结构和半导体集成电路器件的制造方法。 熔丝结构由形成在半导体衬底上的第一互连金属层构成; 在所述第一互连金属层上形成的金属间介电层，其具有暴露所述第一互连金属层的通孔; 通孔插入通孔; 用于保险丝的金属层和连续地沉积在通孔插塞和金属间介电层上的第二互连金属层; 并且露出用于保险丝的金属层的开口面积比第二互连金属层从通孔的厚度的两倍以上。 利用本发明，可以防止在随后的剥离步骤中由通孔堵塞造成的接触故障。 此外，在打开保险丝区域之后形成的钝化层在随后的激光修复过程中防止相邻熔丝之间的短路。

公开(公告)号：US09126892B2

公开(公告)日：2015-09-08

申请号：US12858372

申请日：2010-08-17

申请人： Jong-Kwan Bin ,  Soon-Wook Cha ,  Seung-Jae Lee ,  Jung-Keun Kim ,  Chun-Gun Park

发明人： Jong-Kwan Bin ,  Soon-Wook Cha ,  Seung-Jae Lee ,  Jung-Keun Kim ,  Chun-Gun Park

IPC分类号： H01L51/54 ,  C07C211/61 ,  C07C255/58 ,  C07F7/10 ,  C07C217/92 ,  C07F7/08 ,  C09K11/06 ,  H01L51/00 ,  H01L51/50 ,  H05B33/14

CPC分类号： C07C211/61 ,  C07C217/92 ,  C07C255/58 ,  C07C2603/50 ,  C07F7/081 ,  C09K11/06 ,  C09K2211/1007 ,  C09K2211/1011 ,  C09K2211/1014 ,  H01L51/006 ,  H01L51/5012 ,  H05B33/14

摘要： The present invention relates to a blue fluorescence compound which enables to achieve high brightness, a long lifetime and high efficiency; and an organic electroluminescence device thereof.

摘要翻译： 本发明涉及能够实现高亮度，长寿命和高效率的蓝色荧光化合物; 及其有机电致发光元件。

公开(公告)号：US09099691B2

公开(公告)日：2015-08-04

申请号：US12882125

申请日：2010-09-14

申请人： Po-Jung Hwang ,  Seung-Jae Lee ,  Yoo-Myung Kang ,  Jae-Do Ahn ,  Jae-Min Yang ,  Jeong-Heon Lee ,  Byeong-Yeol Song ,  Jae-Hyun Hwang ,  Sung-Soo Kim ,  Sae-Weon Roh

发明人： Po-Jung Hwang ,  Seung-Jae Lee ,  Yoo-Myung Kang ,  Jae-Do Ahn ,  Jae-Min Yang ,  Jeong-Heon Lee ,  Byeong-Yeol Song ,  Jae-Hyun Hwang ,  Sung-Soo Kim ,  Sae-Weon Roh

IPC分类号： H01M2/26 ,  H01M2/30 ,  H01M2/02 ,  H01M4/70 ,  H01M10/04

CPC分类号： H01M2/0212 ,  H01M2/26 ,  H01M2/266 ,  H01M4/70 ,  H01M10/0413 ,  H01M10/0463

摘要： A rechargeable battery includes an electrode assembly having a plurality of first electrodes each including a first coated region coated with a first active material and a first uncoated region having a first alignment opening and a second alignment opening, a plurality of second electrodes each including a second coated region coated with a second active material and a second uncoated region having a third alignment opening and a fourth alignment opening, a separator between each first coated region and each second coated region; and a case housing the electrode assembly, wherein the first alignment openings are substantially aligned with each other, the second alignment openings are substantially aligned with each other, the third alignment openings are substantially aligned with each other, and the fourth alignment openings are substantially aligned with each other.

摘要翻译： 可再充电电池包括具有多个第一电极的电极组件，每个第一电极包括涂覆有第一活性材料的第一涂覆区域和具有第一对准开口和第二对准开口的第一未涂覆区域，多个第二电极，每个包括第二电极 涂覆有第二活性材料的涂覆区域和具有第三对准开口和第四对准开口的第二未涂覆区域，在每个第一涂覆区域和每个第二涂覆区域之间的隔膜; 以及容纳所述电极组件的壳体，其中所述第一对准开口基本上彼此对准，所述第二对准开口基本上彼此对准，所述第三对准开口基本上彼此对准，并且所述第四对准开口基本对齐 与彼此。