公开(公告)号：US20210391025A1

公开(公告)日：2021-12-16

申请号：US16899965

申请日：2020-06-12

Applicant: SanDisk Technologies LLC

Inventor： Muhammad Masuduzzaman ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26

Abstract: A method comprises determining a verify voltage for a next iteration of a verify operation to be performed on memory cells a first set of memory cells of a selected word line, and determining data states for a second set of memory cells of at least one neighboring word line. The method further comprises determining, based on the data states, a verify voltage configuration that includes bit line voltage biases or sense times, and performing the next iteration of the verify operation on the selected word line by using the verify voltage configuration to iteratively verify whether respective memory cells, of the second set of memory cells, have threshold voltages above the verify voltage, wherein determining the data states, determining the verify voltage configuration, and performing the next iteration are to be repeated until a program stop condition is satisfied.

公开(公告)号：US11107901B2

公开(公告)日：2021-08-31

申请号：US16374330

申请日：2019-04-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu-Chung Lien ,  Jiahui Yuan ,  Deepanshu Dutta

IPC: H01L29/51 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/423 ,  H01L21/28

Abstract: A memory device includes a channel, a control gate electrode, and at least one charge storage element located between the channel and the control gate electrode. The control gate electrode includes a first electrically conductive layer, a second electrically conductive layer and a ferroelectric material layer located between the first electrically conductive layer and the second electrically conductive layer.

公开(公告)号：US20210202011A1

公开(公告)日：2021-07-01

申请号：US16729951

申请日：2019-12-30

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Huai-Yuan Tseng ,  Jiahui Yuan ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C16/04 ,  G11C11/56

Abstract: Method(s) and structure(s) for a two-page read operation are described and provide a multiple page read. The two page read operation provides for reading two pages with in a block without reducing the control gates to a low voltage level. The two page read can read the first page using an incrementing voltage level at discrete steps and starting the second page read at the high state for the control gates from the first page read. The second page read then decrements the control gate voltages level through the steps. This should reduce energy consumption. The two-page read operation will also reduce the time as the time period to reset the control gates to a low state are not required in between the page read operations.

公开(公告)号：US20210134369A1

公开(公告)日：2021-05-06

申请号：US16668675

申请日：2019-10-30

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Muhammad Masuduzzaman ,  Huai-Yuan Tseng ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/10 ,  G11C16/24 ,  G11C11/4074 ,  G11C11/409

Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the fist memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.

公开(公告)号：US10910069B2

公开(公告)日：2021-02-02

申请号：US16909821

申请日：2020-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Murong Lang ,  Zhenming Zhou ,  Deepanshu Dutta

IPC: G11C16/06 ,  G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/1157

Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.

公开(公告)号：US10902925B1

公开(公告)日：2021-01-26

申请号：US16688587

申请日：2019-11-19

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Michael Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/08

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells arranged in strings and connected to word lines overlying one another in a stack. The apparatus includes a control circuit configured to determine whether the memory cells of the block are all programmed. The control circuit determines a boundary word line splitting the word lines into first and second word line sets connected to the memory cells that are respectively programmed and not programmed in response to determining the memory cells of the block are not all programmed. The control circuit applies a delta adjusted read voltage being a default read pass voltage minus a delta voltage to a subset of the second word line set separated from the boundary word line in the stack by at least an offset number of the word lines while reading a first group of memory cells.

公开(公告)号：US20200373355A1

公开(公告)日：2020-11-26

申请号：US16903654

申请日：2020-06-17

Applicant: Sandisk Technologies LLC

Inventor： Yu-Chung Lien ,  Jiahui Yuan ,  Deepanshu Dutta ,  Christopher Petti

IPC: H01L27/24 ,  G11C13/00 ,  H01L27/22 ,  G11C11/16 ,  H01L45/00 ,  H01L43/12 ,  H01L43/02

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive word line layers located over a substrate, and a plurality of vertical memory strings. Each vertical memory string includes a series connection of a memory stack structure and a selector element. Each of the memory stack structures extends through the alternating stack and includes a respective memory film and a respective vertical semiconductor channel. Each of the selector elements includes a two terminal device that is configured to provide at least two different resistivity states.

公开(公告)号：US20200321060A1

公开(公告)日：2020-10-08

申请号：US16909821

申请日：2020-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Murong Lang ,  Zhenming Zhou ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/1157

Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.

公开(公告)号：US20200258571A1

公开(公告)日：2020-08-13

申请号：US16829888

申请日：2020-03-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C16/10

Abstract: Apparatuses, systems, and methods are disclosed for adjusting a programming setting such as a programming voltage of a set of non-volatile storage cells, such as an SLC NAND array. The non-volatile storage cells may be arranged into a plurality of word lines. A subset of the non-volatile storage cells may be configured to store a programming setting. An on-die controller may be configured to read the programming setting from the setting subset, and write data to the non-volatile storage cells, using the programming setting. The on-die controller may further be configured to determine that the programming setting causes suboptimal programming of one or more of the non-volatile storage cells, and in response to the determination, store a revised programming setting on the setting subset.

公开(公告)号：US20200243138A1

公开(公告)日：2020-07-30

申请号：US16842112

申请日：2020-04-07

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/04 ,  G11C11/56 ,  G06F11/10 ,  G11C16/10 ,  G11C16/08 ,  G06F11/18

Abstract: Techniques for fast programming and read operations for memory cells. A first set of bit lines is connected to a first set of NAND strings and is interleaved with a second set of bit lines connected to a second set of NAND strings. The first set of NAND strings can be programmed by driving a voltage on the first set of bit lines while floating a voltage on the second set of bit lines, to reduce an inter-bit line capacitance and provide a relatively high access speed and a relatively low storage density (e.g., bits per memory cell). The second set of NAND strings can be programmed by concurrently driving a voltage on the first and second sets of bit lines, to provide a relatively low access speed and a relatively high storage density.