公开(公告)号：US12057157B2

公开(公告)日：2024-08-06

申请号：US17690332

申请日：2022-03-09

Applicant: SanDisk Technologies LLC

Inventor： Jiahui Yuan ,  Kai Kirk ,  Yu-Chung Lien

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/4076

CPC classification number: G11C11/4096 ,  G11C11/4074 ,  G11C11/4076

Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine whether the apparatus is in low power mode; in response to determining that the apparatus is in low power mode, perform a normal order read operation on a set of memory cells of the plurality of memory cells; and in response to determining that the apparatus is not in low power mode, perform a reverse order read operation on the set of memory cells of the plurality of memory cells.

公开(公告)号：US11887670B2

公开(公告)日：2024-01-30

申请号：US17406224

申请日：2021-08-19

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Deepanshu Dutta ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04 ,  G11C16/24

CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: Apparatuses and techniques are described for controlling a bit line pre-charge voltage in a program operation based on a number of bits per cell, with a goal to reduce peak current consumption. In one aspect, the ramp up of a bit line voltage to an inhibit level is optimized according to the number of bits per cell. The ramp up can involve increasing the bit line voltage from an initial level to a target voltage at a regulated rate, then increasing the bit line voltage from the target voltage to a final voltage at an unregulated rate. In one approach, the regulated ramp rate is less for single-level cell programming compared to multi-level cell programming. The target voltage can also be optimized based on the number of bis per cell.

公开(公告)号：US11837296B2

公开(公告)日：2023-12-05

申请号：US17505179

申请日：2021-10-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu-Chung Lien ,  Jiahui Yuan ,  Ohwon Kwon

IPC: G11C16/04 ,  G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2225/06506 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.

公开(公告)号：US20230282295A1

公开(公告)日：2023-09-07

申请号：US17685113

申请日：2022-03-02

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Xue Bai Pitner ,  Ken Oowada

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/3495 ,  G11C16/102 ,  G11C16/26 ,  G11C16/08 ,  G11C16/0433

Abstract: A method for programming a target memory cell of a memory array of a non-volatile memory system, the method comprises determining a total number of erase/programming (EP) cycles that were applied previously to the memory cell and, (1) if the determined total number of cycles does not exceed a threshold value, applying an asymmetric programming scheme, and, (2) if the determined total number of cycles exceeds the threshold value, applying a symmetric programming scheme. Further, a magnitude of a boosting voltage bias (VPASS) that is to be applied to an unselected word line may be determined according to the determined total number of erase/programming (EP) cycles.

公开(公告)号：US20230253047A1

公开(公告)日：2023-08-10

申请号：US17665824

申请日：2022-02-07

Applicant: SanDisk Technologies LLC

Inventor： Xue Pitner ,  Yu-Chung Lien ,  Sarath Puthenthermadam ,  Sujjatul Islam

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11556

Abstract: A non-volatile semiconductor memory device, described herein, comprises non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to, during a program iteration of a program operation, determine whether a program voltage level of the program iteration exceeds a threshold program voltage level and in response to the determination, identify a set of voltage levels to apply to a source line connected to a set of the non-volatile storage elements. The one or more control circuits are further configured to perform the program iteration of the program operation on the set of non-volatile storage elements, where the program iteration includes applying the set of voltage levels to the source line.

公开(公告)号：US20230120352A1

公开(公告)日：2023-04-20

申请号：US17505179

申请日：2021-10-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu-Chung Lien ,  Jiahui Yuan ,  Ohwon Kwon

IPC: G11C16/34 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.

公开(公告)号：US20230056891A1

公开(公告)日：2023-02-23

申请号：US17406224

申请日：2021-08-19

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Deepanshu Dutta ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/04 ,  G11C16/30

Abstract: Apparatuses and techniques are described for controlling a bit line pre-charge voltage in a program operation based on a number of bits per cell, with a goal to reduce peak current consumption. In one aspect, the ramp up of a bit line voltage to an inhibit level is optimized according to the number of bits per cell. The ramp up can involve increasing the bit line voltage from an initial level to a target voltage at a regulated rate, then increasing the bit line voltage from the target voltage to a final voltage at an unregulated rate. In one approach, the regulated ramp rate is less for single-level cell programming compared to multi-level cell programming. The target voltage can also be optimized based on the number of bis per cell.

公开(公告)号：US11373710B1

公开(公告)日：2022-06-28

申请号：US17165703

申请日：2021-02-02

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  Yu-Chung Lien ,  Mark Murin ,  Mark Shlick

IPC: G11C5/14 ,  G11C16/30 ,  G11C16/08 ,  G11C8/18 ,  G11C7/22 ,  G11C11/4076 ,  G11C16/10

Abstract: Time division peak power management in non-volatile memory systems is disclosed. The memory system has a memory controller and a number of semiconductor dies. Each die is assigned a time slot in which to perform high current portions of memory operations. The memory controller provides an external clock to each die. Each die tracks repeating time slots based on the external clock. The memory controller may synchronize this tracking. If a die is about to perform a high current portion of a memory operation, the die checks to determine if its allocated slot has been reached. If not, the die halts the memory operation until its allocated time slot is reached. When the allocated time slot is reached, the halted memory operation is resumed at the high current portion. Therefore, the high current portion of the memory operation occurs during the allocated time slot.

公开(公告)号：US11315648B2

公开(公告)日：2022-04-26

申请号：US16915663

申请日：2020-06-29

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Dengtao Zhao ,  Huai-Yuan Tseng

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/30

Abstract: An apparatus includes a memory controller configured to apply selected one or ones of the program verify voltage levels to a single tier of memory cells. A memory controller is configured to: program data into the plurality of memory cells; and perform a program verify operation across multiple voltage levels with a first voltage level of the program verify operation being applied to a single tier that represents all of the tiers in the memory group and a second voltage level of the program verify operation being applied to multiple tiers, wherein the first voltage level is less than the second voltage level. In embodiments, less than all of the tiers, e.g., two or four tiers, can be used in the program verify to represent all of the tires.

公开(公告)号：US11226772B1

公开(公告)日：2022-01-18

申请号：US16912381

申请日：2020-06-25

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Mark Murin ,  Hua-Ling Cynthia Hsu ,  Tomer Eliash ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/32 ,  H01L25/065 ,  G11C16/04

Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.