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    Increasing the surface area of a memory cell capacitor
    123.
    发明授权
    Increasing the surface area of a memory cell capacitor 有权
    增加存储单元电容器的表面积

    公开(公告)号：US08232588B2

    公开(公告)日：2012-07-31

    申请号：US12749389

    申请日：2010-03-29

    申请人： Brian S. Doyle ,  Robert S. Chau ,  Vivek De ,  Suman Datta ,  Dinesh Somasekhar

    发明人： Brian S. Doyle ,  Robert S. Chau ,  Vivek De ,  Suman Datta ,  Dinesh Somasekhar

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852

    摘要： Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.

    摘要翻译： 描述了增加存储单元电容器的表面积的方法和装置。 形成了沉积在基板上的第一绝缘层上的第二绝缘层中的开口。 衬底具有翅片。 第一绝缘层沉积在邻近鳍片的衬底上。 第二绝缘层上的开口形成在鳍上。 第一导电层沉积在第二绝缘层和鳍上。 第三绝缘层沉积在第一导电层上。 在第三绝缘层上沉积第二导电层。 第二导电层填充开口。 第二导电层是提供与上金属层的互连。 从第二绝缘层的顶表面去除第二导电层，第三绝缘层和第一导电层的部分。

    NONPLANAR SEMICONDUCTOR DEVICE WITH PARTIALLY OR FULLY WRAPPED AROUND GATE ELECTRODE AND METHODS OF FABRICATION
    128.
    发明申请
    NONPLANAR SEMICONDUCTOR DEVICE WITH PARTIALLY OR FULLY WRAPPED AROUND GATE ELECTRODE AND METHODS OF FABRICATION 有权
    非门式半导体器件，部分或完全包裹在门电极和制造方法

    公开(公告)号：US20110020987A1

    公开(公告)日：2011-01-27

    申请号：US12893753

    申请日：2010-09-29

    申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    IPC分类号： H01L21/336 ,  H01L21/762

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795

    摘要： A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

    摘要翻译： 描述了非平面半导体器件及其制造方法。 非平面半导体器件包括半导体本体，该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。 在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。 栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。 在栅电极的相对侧的半导体本体中形成一对源/漏区。