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    Method for Manufacturing an Anchor-Shaped Backside Via
    122.
    发明申请
    Method for Manufacturing an Anchor-Shaped Backside Via 有权

    公开(公告)号：US20220013453A1

    公开(公告)日：2022-01-13

    申请号：US16926447

    申请日：2020-07-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang

    IPC: H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/768

    Abstract: A method includes providing a fin, an isolation structure, and first and second source/drain (S/D) features over the fin; forming an etch mask covering a first portion and exposing a second portion of the fin; removing the second portion of the fin, resulting in a first trench; filling the first trench with a first dielectric feature; removing the etch mask; and applying etching process(es) to remove the first portion of the fin and to partially recess the first S/D feature. The etching process(es) includes an isotropic etching tuned selective to materials of the first S/D feature and not materials of the isolation structure and the first dielectric feature, resulting in a second trench under the first S/D feature and having a gap between a bottom surface of the first S/D feature and a top surface of the isolation structure. The method further includes forming a via in the second trench.

    SELF-ALIGNED CONTACT STRUCTURES
    125.
    发明申请
    SELF-ALIGNED CONTACT STRUCTURES 有权

    公开(公告)号：US20210384316A1

    公开(公告)日：2021-12-09

    申请号：US16895604

    申请日：2020-06-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L29/66 ,  H01L21/768

    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

    Semiconductor devices with backside power distribution network and frontside through silicon via
    128.
    发明授权
    Semiconductor devices with backside power distribution network and frontside through silicon via 有权

    公开(公告)号：US11158580B2

    公开(公告)日：2021-10-26

    申请号：US16656715

    申请日：2019-10-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kam-Tou Sio ,  Cheng-Chi Chuang ,  Chia-Tien Wu ,  Jiann-Tyng Tzeng ,  Shih-Wei Peng ,  Wei-Cheng Lin

    IPC: H01L23/495 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48

    Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the third interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.

    Structure and formation method of interconnection structure of semiconductor device
    130.
    发明授权
    Structure and formation method of interconnection structure of semiconductor device 有权

    公开(公告)号：US11088020B2

    公开(公告)日：2021-08-10

    申请号：US15691035

    申请日：2017-08-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Li-Lin Su ,  Shin-Yi Yang ,  Cheng-Chi Chuang ,  Hsin-Ping Chen

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a conductive feature in a first dielectric layer. The semiconductor device structure also includes an etching stop layer over the first dielectric layer and a second dielectric layer over the etching stop layer. The semiconductor device structure further includes a conductive via in the etching stop layer and the second dielectric layer. In addition, the semiconductor device structure includes a conductive line over the conductive via. The semiconductor device structure also includes a first barrier liner covering the bottom surface of the conductive line. The semiconductor device structure further includes a second barrier liner surrounding sidewalls of the conductive line and the conductive via. The conductive line and the conductive via are confined in the first barrier liner and the second barrier liner.

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