公开(公告)号：US20070117358A1

公开(公告)日：2007-05-24

申请号：US11622490

申请日：2007-01-12

Applicant: Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

Inventor： Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

IPC: H01L27/12 ,  H01L21/20

CPC classification number: C30B25/00 ,  C30B29/06 ,  C30B29/52 ,  Y10S438/933

Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

Abstract translation: 提供了形成均匀厚度的外延层的方法以改善表面平坦度。 首先提供衬底，然后通过外延在衬底上形成Si基层。 通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

公开(公告)号：US20070093046A1

公开(公告)日：2007-04-26

申请号：US11562522

申请日：2006-11-22

Applicant: Wen-Chin Lee

Inventor： Wen-Chin Lee

IPC: H01L21/3205

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L29/78

Abstract: Disclosed is a method of manufacturing microelectronic devices including forming a silicon substrate with first and second wells of different dopant characteristics, forming a first strained silicon-germanium-carbon layer of a first formulation proximate to the first well, and forming a second strained silicon-germanium-carbon layer of a second formulation distinct from the first formulation proximate to the second well. Capping and insulating layers, gate structures, spacers, and sources and drains are then formed, thereby creating a CMOS device with independently strained channels.

Abstract translation: 公开了一种制造微电子器件的方法，包括用具有不同掺杂剂特性的第一和第二阱形成硅衬底，形成靠近第一阱的第一制剂的第一应变硅 - 锗 - 碳层，以及形成第二应变硅 - 不同于靠近第二孔的第一制剂的第二制剂的锗 - 碳层。 然后形成封盖和绝缘层，栅极结构，间隔物以及源极和漏极，从而产生具有独立应变通道的CMOS器件。

公开(公告)号：US20070045849A1

公开(公告)日：2007-03-01

申请号：US11216512

申请日：2005-08-31

Applicant: Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L23/48

CPC classification number: H01L29/045 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The channel of a MOSFET is selectively stressed by selectively stressing the silicide layers on the gate electrode and the source/drain. Stress in the silicide layer is selectively produced by orienting the larger dimensions of the silicide grains in a first direction and the smaller dimensions in a second, perpendicular direction, with one of the directions being parallel to the direction of carrier movement in the channel and the other direction being perpendicular thereto.

Abstract translation: 通过选择性地施加栅极电极和源极/漏极上的硅化物层来选择性地施加MOSFET的沟道。 硅化物层中的应力选择性地通过使第一方向上的硅化物颗粒的尺寸取向，并且在第二垂直方向上定向较小的尺寸，其中一个方向平行于通道中的载体移动方向，并且 其他方向与其垂直。

公开(公告)号：US07145166B2

公开(公告)日：2006-12-05

申请号：US10922087

申请日：2004-08-19

Applicant: Wen-Chin Lee

Inventor： Wen-Chin Lee

IPC: H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L29/78

Abstract: Disclosed is a method of manufacturing microelectronic devices including forming a silicon substrate with first and second wells of different dopant characteristics, forming a first strained silicon-germanium-carbon layer of a first formulation proximate to the first well, and forming a second strained silicon-germanium-carbon layer of a second formulation distinct from the first formulation proximate to the second well. Capping and insulating layers, gate structures, spacers, and sources and drains are then formed, thereby creating a CMOS device with independently strained channels.

Abstract translation: 公开了一种制造微电子器件的方法，包括用具有不同掺杂剂特性的第一和第二阱形成硅衬底，形成靠近第一阱的第一制剂的第一应变硅 - 锗 - 碳层，以及形成第二应变硅 - 不同于靠近第二孔的第一制剂的第二制剂的锗 - 碳层。 然后形成封盖和绝缘层，栅极结构，间隔物以及源极和漏极，从而产生具有独立应变通道的CMOS器件。

公开(公告)号：US20060255365A1

公开(公告)日：2006-11-16

申请号：US11483913

申请日：2006-07-10

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L31/00

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

公开(公告)号：US07112495B2

公开(公告)日：2006-09-26

申请号：US10729095

申请日：2003-12-05

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/76

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

Abstract translation: 半导体芯片包括其中设置有第一和第二有源区的半导体衬底126。 电阻器124形成在第一有源区域中，并且电阻器124包括形成在两个端子136之间的掺杂区域128。 应变通道晶体管132形成在第二有源区中。 该晶体管包括第一和第二应力源141，该第一和第二应力器141形成在与基片相反的相邻的应变通道区域143之间。

公开(公告)号：US07105908B2

公开(公告)日：2006-09-12

申请号：US10852324

申请日：2004-05-24

Applicant: Wen-Chin Lee ,  Yee-Chia Yeo

Inventor： Wen-Chin Lee ,  Yee-Chia Yeo

IPC: H01L29/00

CPC classification number: H01L27/11 ,  H01L27/1104

Abstract: A semiconductor device comprises a substrate. In addition, the semiconductor device comprises an active region and an isolation region. The active region is in the substrate and comprises a semiconductor material. The isolation region is also in the substrate, adjacent the active region and comprises an insulating material. The active region and isolation region form a surface having a step therein. The semiconductor further comprises a dielectric material formed over the step. The dielectric material has a dielectric constant greater than about 8.

公开(公告)号：US20060177997A1

公开(公告)日：2006-08-10

申请号：US11377105

申请日：2006-03-16

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

IPC: H01L21/20

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating an integrated circuit is provided. A first gate dielectric portion is formed on a substrate in a first transistor region. The first gate dielectric portion includes a first high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. A second gate dielectric portion is formed on the substrate in a second transistor region. The second gate dielectric portion includes the first high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness is different than the first equivalent silicon oxide thickness.

Abstract translation: 提供一种制造集成电路的方法。 第一栅介质部分形成在第一晶体管区域中的衬底上。 第一栅介质部分包括第一高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 在第二晶体管区域中的衬底上形成第二栅介质部分。 第二栅介质部分包括第一高电容率介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度不同于第一等效氧化硅厚度。

公开(公告)号：US07078723B2

公开(公告)日：2006-07-18

申请号：US10819250

申请日：2004-04-06

Applicant: Chuan-Yi Lin ,  Wen-Chin Lee ,  Sun-Jay Chang ,  Shien-Yang Wu

Inventor： Chuan-Yi Lin ,  Wen-Chin Lee ,  Sun-Jay Chang ,  Shien-Yang Wu

IPC: H01L29/06

CPC classification number: H01L29/785 ,  H01L21/2236 ,  H01L21/823412 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/78687

Abstract: A microelectronic device includes a substrate, and a patterned feature located over the substrate and a plurality of doped regions, wherein the patterned feature includes at least one electrode. The microelectronic device includes at least one sill region for the enhancement of electron and/or hole mobility.

Abstract translation: 微电子器件包括衬底和位于衬底上的图案化特征和多个掺杂区域，其中图案化特征包括至少一个电极。 微电子器件包括用于增强电子和/或空穴迁移率的至少一个基底区域。

公开(公告)号：US20060114228A1

公开(公告)日：2006-06-01

申请号：US10996419

申请日：2004-11-26

Applicant: Wen-Chin Lee ,  Shang-Hao Chen

Inventor： Wen-Chin Lee ,  Shang-Hao Chen

IPC: G09G5/08

CPC classification number: G06F3/0346 ,  G05G9/047 ,  G06F3/0362

Abstract: A magnetic oscillation metric controller with return design comprised of a scrolling wheel mechanism, a dancer, a permanent magnet, a Hall sensor and a return structure to drive the permanent magnet by oscillation of the scrolling wheel mechanism to generate signals of changed magnetic fields resulted from displacement for achieving metric control purpose; and the return structure including an elastic stick to facilitate return after lateral or longitudinal displacement.

Abstract translation: 具有返回设计的磁振荡度量控制器包括滚动轮机构，浮动机构，永磁体，霍尔传感器和返回结构，以通过滚动轮机构的振荡来驱动永磁体，以产生由 实现度量控制目的的排量 并且返回结构包括弹性棒，以便于在横向或纵向位移之后返回。