公开(公告)号：US10546964B2

公开(公告)日：2020-01-28

申请号：US13677361

申请日：2012-11-15

Applicant: Shih-Wei Chen ,  Wen-Chin Lee ,  Wen-Tsai Yen ,  Chung-Hsien Wu ,  Kuan-Chu Chen

Inventor： Shih-Wei Chen ,  Wen-Chin Lee ,  Wen-Tsai Yen ,  Chung-Hsien Wu ,  Kuan-Chu Chen

IPC: H01L31/032 ,  H01L31/0749 ,  H01L31/0392 ,  H01L31/0224

Abstract: A solar cell with a molybdenum back electrode layer and a molybdenum selenide ohmic contact layer over the molybdenum back electrode, is provided. The molybdenum selenide layer includes an accurately controlled thickness. A distinct interface exists between the molybdenum back electrode layer and the molybdenum silicide layer. The molybdenum silicide layer is produced by forming a molybdenum layer or a molybdenum nitride layer or a molybdenum oxide layer over an initially formed molybdenum layer such that an interface exists between the two layers. A selenization and sulfurization process is carried out to selectively convert the molybdenum-containing layer to molybdenum selenide but not the original molybdenum back electrode layer which remains as a molybdenum layer.

公开(公告)号：US08536619B2

公开(公告)日：2013-09-17

申请号：US11702390

申请日：2007-02-05

Applicant: Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

Inventor： Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

IPC: H01L29/66

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor structure includes a semiconductor substrate having a top surface; a gate stack on the semiconductor substrate; and a stressor in the semiconductor substrate and adjacent the gate stack. The stressor comprises at least a first portion with a first top surface lower than the top surface of the semiconductor substrate.

Abstract translation: 半导体结构包括具有顶表面的半导体衬底; 半导体衬底上的栅极堆叠; 以及半导体衬底中的紧邻栅叠层的应力器。 所述应力器至少包括具有比所述半导体衬底的顶表面低的第一顶表面的第一部分。

公开(公告)号：US08236658B2

公开(公告)日：2012-08-07

申请号：US12477757

申请日：2009-06-03

Applicant: Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

Inventor： Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

Abstract: A semiconductor device and method for fabricating a semiconductor device providing reduced short channel effects is disclosed. The method comprises providing a substrate comprising a first material; forming at least one gate stack over the substrate; forming one or more recesses in the substrate, wherein the one or more recesses define at least one source region and at least one drain region; and forming a pocket, a first layer comprising a second material, and a second layer comprising a third material in the one or more recesses, the pocket being disposed between the first layer and the substrate.

Abstract translation: 公开了一种用于制造提供减小的短通道效应的半导体器件的半导体器件和方法。 该方法包括提供包括第一材料的基底; 在所述衬底上形成至少一个栅极堆叠; 在所述衬底中形成一个或多个凹槽，其中所述一个或多个凹部限定至少一个源极区域和至少一个漏极区域; 并且形成袋，包含第二材料的第一层和在所述一个或多个凹部中包含第三材料的第二层，所述袋设置在所述第一层和所述基底之间。

公开(公告)号：US08154107B2

公开(公告)日：2012-04-10

申请号：US11703365

申请日：2007-02-07

Applicant: Chung-Hu Ke ,  Chih-Hsin Ko ,  Wen-Chin Lee

Inventor： Chung-Hu Ke ,  Chih-Hsin Ko ,  Wen-Chin Lee

IPC: H01L23/58

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66606 ,  H01L29/78 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having at least one transistor covered by an ultra-stressor layer, and method for fabricating such a device. In an NMOS device, the ultra-stressor layer includes a tensile stress film over the source and drain regions, and a compressive stress film over the poly region. In a PMOS device, the ultra-stressor layer includes a compressive stress film over the source and drain regions and a tensile stress film over the poly region. In a preferred embodiment, the semiconductor device includes a PMOS transistor and an NMOS transistor forming a CMOS device and covered with an ultra stressor layer.

Abstract translation: 具有被超应力层覆盖的至少一个晶体管的半导体器件及其制造方法。 在NMOS器件中，超应力层包括源极和漏极区域上的拉伸应力膜，以及多个区域上的压应力膜。 在PMOS器件中，超应力层包括源极和漏极区域上的压缩应力膜和在多个区域上的拉伸应力膜。 在优选实施例中，半导体器件包括PMOS晶体管和形成CMOS器件并被超压应力层覆盖的NMOS晶体管。

公开(公告)号：US20110027959A1

公开(公告)日：2011-02-03

申请号：US12898421

申请日：2010-10-05

Applicant: Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

Inventor： Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

IPC: H01L21/336

CPC classification number: H01L29/7391 ,  H01L21/26586

Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

Abstract translation: 半导体器件包括沟道区; 沟道区上的栅极电介质; 位于栅极电介质上的栅电极; 以及与栅极电介质相邻的第一源极/漏极区域。 第一源极/漏极区域是第一导电类型。 沟道区域和第一源极/漏极区域中的至少一个包括超晶格结构。 所述半导体器件还包括与所述第一源极/漏极区域相比在所述沟道区域的相对侧上的第二源极/漏极区域。 第二源极/漏极区域是与第一导电类型相反的第二导电类型。 最多，第一源极/漏极区域和第二源极/漏极区域中的一个包括附加的超晶格结构。

公开(公告)号：US20100308379A1

公开(公告)日：2010-12-09

申请号：US12477757

申请日：2009-06-03

Applicant: Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

Inventor： Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

Abstract: A semiconductor device and method for fabricating a semiconductor device providing reduced short channel effects is disclosed. The method comprises providing a substrate comprising a first material; forming at least one gate stack over the substrate; forming one or more recesses in the substrate, wherein the one or more recesses define at least one source region and at least one drain region; and forming a pocket, a first layer comprising a second material, and a second layer comprising a third material in the one or more recesses, the pocket being disposed between the first layer and the substrate.

Abstract translation: 公开了一种用于制造提供减小的短通道效应的半导体器件的半导体器件和方法。 该方法包括提供包括第一材料的基底; 在所述衬底上形成至少一个栅极堆叠; 在所述衬底中形成一个或多个凹槽，其中所述一个或多个凹部限定至少一个源极区域和至少一个漏极区域; 并且形成袋，包含第二材料的第一层和在所述一个或多个凹部中包含第三材料的第二层，所述袋设置在所述第一层和所述基底之间。

公开(公告)号：US07737532B2

公开(公告)日：2010-06-15

申请号：US11220176

申请日：2005-09-06

Applicant: Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

Inventor： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

IPC: H01L29/04

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/785

Abstract: A CMOS device is provided. A semiconductor device comprises a substrate, the substrate having a first region and a second region, the first region having a first crystal orientation represented by a family of Miller indices comprising {i,j,k}, the second region having a second crystal orientation represented a family of Miller indices comprising {l,m,n}, wherein l2+m2+n2>i2+j2+k2. Alternative embodiments further comprise an NMOSFET formed on the first region, and a PMOSFET formed on the second region. Embodiments further comprise a Schottky contact formed with at least one of a the NMOSFET or PMOSFET.

Abstract translation: 提供CMOS器件。 半导体器件包括衬底，衬底具有第一区域和第二区域，第一区域具有由包括{i，j，k}的米勒指数族代表的第一晶体取向，第二区域具有第二晶体取向 表示包括{l，m，n}的米勒指数族，其中l2 + m2 + n2> i2 + j2 + k2。 替代实施例还包括形成在第一区域上的NMOSFET和形成在第二区域上的PMOSFET。 实施例还包括由NMOSFET或PMOSFET中的至少一个形成的肖特基接触。

公开(公告)号：US07592619B2

公开(公告)日：2009-09-22

申请号：US11622490

申请日：2007-01-12

Applicant: Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

Inventor： Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

IPC: H01L29/15

CPC classification number: C30B25/00 ,  C30B29/06 ,  C30B29/52 ,  Y10S438/933

Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

Abstract translation: 提供了形成均匀厚度的外延层的方法以改善表面平坦度。 首先提供衬底，然后通过外延在衬底上形成Si基层。 通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

公开(公告)号：US07582934B2

公开(公告)日：2009-09-01

申请号：US12040877

申请日：2008-03-01

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

IPC: H01L27/12

CPC classification number: H01L29/66772 ,  H01L27/1203 ,  H01L29/78618 ,  Y10S257/90

Abstract: A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.

Abstract translation: 半导体器件包括覆盖介电层的半导体台面，形成在半导体台面上的栅叠层，以及形成在半导体台面周围的隔离间隔物，并填充半导体台面的边缘处的任何底切区域。

公开(公告)号：US07511348B2

公开(公告)日：2009-03-31

申请号：US11717450

申请日：2007-03-13

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

IPC: H01L29/76

CPC classification number: H01L21/823807 ,  H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4933 ,  H01L29/517 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7845

Abstract: The channels of first and second CMOS transistors can be selectively stressed. A gate structure of the first transistor includes a stressor that produces stress in the channel of the first transistor. A gate structure of the second transistor is disposed in contact with a layer of material that produces stress in the channel of the second transistor.

Abstract translation: 第一和第二CMOS晶体管的通道可以选择性地受到压力。 第一晶体管的栅极结构包括在第一晶体管的沟道中产生应力的应力源。 第二晶体管的栅极结构设置成与在第二晶体管的沟道中产生应力的材料层接触。