Abstract:
A battery management system includes: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; and a first slave BMIC device and a second slave BMIC device that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device is coupled to the master BMIC through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device and the second slave BMIC device are configured to be coupled to a first battery pack and a second battery pack, respectively.
Abstract:
A read circuit for capacitive sensors such as a MEMS microphones includes a sensor node configured to be coupled to a capacitive sensor to apply a bias voltage to the sensor and sense the capacitance value of the sensor wherein the voltage at the sensor node is indicative of the capacitance value of the capacitive sensor. A switch is provided between the sensor node and the intermediate node. A shock detector coupled to the sensor node and the switch asserts a shock signal to make the switch conductive in response to a shock applied to the capacitive sensor, and de-asserts the shock signal to make the switch non-conductive with a delay after the end of the shock applied to the capacitive sensor.
Abstract:
In an embodiment, a method for controlling a synchronous rectifier (SR) transistor of a flyback converter includes: determining a first voltage across conduction terminals of the SR transistor; asserting a turn-on signal when a body diode of the SR transistor is conducting current; asserting a turn-off signal when current flowing through the conduction terminals of the SR transistor decreases below a first threshold; generating a gating signal based on an output voltage of the flyback converter and on the first voltage; turning on the SR transistor based on the turn-on signal and on the gating signal; and turning off the SR transistor based on the turn-off signal.
Abstract:
In an embodiment a method for detecting an activity of a first eye of a user using glasses includes acquiring, by a controller and through first and second electrodes, a first electrostatic charge variation signal indicative of a difference between the electrostatic charge variations detected by the first and the second electrodes, verifying, by the controller, a presence of one or more blink patterns in the first electrostatic charge variation signal, each blink pattern being indicative of a respective click or of a respective blink, the click being a voluntary blink of the first eye and the blink being an involuntary blink of the first eye, when the first electrostatic charge variation signal has the one or more blink patterns, determining, by the controller for each blink pattern, whether a first condition is verified, when the first condition is not verified, detecting, by the controller, a respective blink and when the first condition is verified, detecting, by the controller, a respective click.
Abstract:
A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/output register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/output register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a commands, and resumes the normal operating mode in response to a wake-up events.
Abstract:
A method for accessing memory cells in an array of memory cells storing respective data signals, wherein memory cells in the array of memory cells have a first, resp. second, node selectively couplable to respective bitline branches in a first, resp. second, set of bitline branches, wherein the first and the second set of bitline branches provide at least one bitline capacitance configured to store a bias level of charge in response to being charged.
Abstract:
A communication network comprises a plurality of electronic devices coupled via a plurality of communication links. The communication links comprise links over a first physical medium and links over a second physical medium. A method of operating the network comprises issuing, at an originator device, a path request message directed towards a destination device, transmitting the path request message from the originator device to the destination device through a first set of intermediate devices via a forward sequence of links, issuing, at the destination device, a path reply message directed towards the originator device, and transmitting the path reply message from the destination device to the originator device through a second set of intermediate devices via a reverse sequence of links.
Abstract:
An embodiment power-on-reset circuit, having a power supply input to receive a power supply voltage, generates a reset signal with a value switching upon the power supply voltage crossing a POR detection level. The power-on-reset circuit has: a PTAT stage having a left branch and a right branch and generating a current equilibrium condition between the currents circulating in the left and right branches upon the power supply voltage reaching the POR detection level; and an output stage coupled to the PTAT stage and generating the reset signal, with the value switching at the occurrence of the current equilibrium condition for the PTAT stage. The power-on-reset circuit further comprises a detection-level generation stage, coupled to the PTAT stage as a central branch thereof to define the value of the POR detection level.
Abstract:
A voltage reference circuit includes a first circuit block configured to generate a proportional to absolute temperature current, the first circuit block comprising a current mirror amplifier, a second circuit block coupled to the first circuit block and configured to generated a complimentary to absolute temperature current, and a third circuit block coupled to both the first circuit block and the second circuit block. The second circuit block includes a multi-stage common-source amplifier. The third circuit block is configured to combine the proportional to absolute temperature current and the complimentary to absolute temperature current to generate a reference voltage at an output of the voltage reference circuit.
Abstract:
A switching converter converts an input signal to a regulated output signal using a switch and a transformer with a primary winding and a secondary winding. A wake up management circuit receives a transformer demagnetization signal and forces by wake up pulses the switch on when the switching converter operates in a burst mode. Sampled values of the transformer demagnetization signal are received. A setting circuit sets a first peak value of the current of the primary winding. A comparison circuit compare the sampled values with a voltage threshold and the preceding sampled value. In response thereto, the first peak value of the primary winding current is either maintained or a new peak value is set.