公开(公告)号：US08487572B2

公开(公告)日：2013-07-16

申请号：US13246973

申请日：2011-09-28

Applicant: Lynn R. Kern ,  James P. McFarland

Inventor： Lynn R. Kern ,  James P. McFarland

IPC: H02P6/00

CPC classification number: H02P6/182

Abstract: A control method for a brushless, three-phase DC motor. The motor may include a plurality of electromagnets and a rotor. A voltage induced by rotation of a rotor may be sampled at an expected zero crossing value to produce a first sampled voltage value. An average of a plurality of sampled voltage values, including voltage values sampled at a plurality of prior expected zero crossing values, may be calculated. A delta zero crossing error may be calculated. The delta zero crossing error may be calculated based on a difference between the first sampled voltage value and the calculated average. The plurality of electromagnets may be commutated. Commutation timing for the plurality of electromagnets may be determined based at least in part on the delta zero crossing error.

Abstract translation: 一种无刷三相直流电动机的控制方法。 马达可以包括多个电磁体和转子。 可以以预期的过零值对由转子引起的电压进行采样，以产生第一采样电压值。 可以计算多个采样电压值的平均值，包括在多个先前预期过零值处采样的电压值。 可以计算Δ过零误差。 可以基于第一采样电压值和所计算的平均值之间的差来计算Δ过零误差。 多个电磁体可以被换向。 可以至少部分地基于增量零交叉误差来确定多个电磁体的换向定时。

公开(公告)号：US08368334B2

公开(公告)日：2013-02-05

申请号：US12620726

申请日：2009-11-18

Applicant: Lynn R. Kern ,  Scott C. McLeod ,  Kenneth W. Gay

Inventor： Lynn R. Kern ,  Scott C. McLeod ,  Kenneth W. Gay

IPC: H02P6/00

CPC classification number: H02P6/182 ,  F04D27/004 ,  H02P27/085

Abstract: A control method for a brushless, three-phase DC motor. A voltage induced by rotation of a rotor may be sampled at a first expected zero crossing value to produce a first sampled voltage value. An average of a plurality of sampled voltage values, including voltage values sampled at a plurality of prior expected zero crossing values and the first sampled voltage value, may be calculated. The first sampled voltage value may be subtracted from the calculated average to produce a delta zero crossing error. A pulse-width modulation duty cycle may be adjusted based on the delta zero crossing error. The pulse-width modulation duty cycle may be used to control a rotational velocity of the rotor.

Abstract translation: 一种无刷三相直流电动机的控制方法。 可以在第一预期过零值处对由转子旋转引起的电压进行采样，以产生第一采样电压值。 可以计算多个采样电压值的平均值，包括在多个先前预期过零值处采样的电压值和第一采样电压值。 可以从计算的平均值中减去第一采样电压值，以产生Δ零交叉误差。 脉冲宽度调制占空比可以根据增量零交叉误差进行调整。 脉冲宽度调制占空比可用于控制转子的旋转速度。

公开(公告)号：US08352657B2

公开(公告)日：2013-01-08

申请号：US13246365

申请日：2011-09-27

Applicant: Mark R. Bohm

Inventor： Mark R. Bohm

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F1/3203 ,  G06F1/3253 ,  G06F2213/0042 ,  Y02D10/151

Abstract: A simple data transfer mechanism may be combined with static state bus signaling to replace a USB with a digital serial interconnect bus (DSIB). This may eliminate various pull-up/pull-down resistors required in USB, and enable the DSIB to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The DSIB may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The DSIB may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.

Abstract translation: 简单的数据传输机制可以与静态总线信号组合，以用数字串行互连总线（DSIB）代替USB。 这可以消除USB中所需的各种上拉/下拉电阻，并且当总线处于空闲状态或数据传输状态时，使DSIB能够很少或没有泄漏电流工作。 所有必需的功能可以仅使用两个信号引脚来实现。 DSIB还可以为不需要PLL的高速USB启用硅解决方案，因为时钟可能由传输源提供，因此可能不需要从串行数据流中恢复。 DSIB可以通过使设计人员能够移除模拟PHY并用串行数字I / O传输机制替代它，同时保留IP的USB定时器以及其他协议特定功能，为USB芯片提供了一个简单的重用机制。

公开(公告)号：US08241008B2

公开(公告)日：2012-08-14

申请号：US12393571

申请日：2009-02-26

Applicant: Chao-Ming Tsai ,  Lynn R. Kern

Inventor： Chao-Ming Tsai ,  Lynn R. Kern

IPC: F04B49/10 ,  F04B49/00

CPC classification number: F04D27/00

Abstract: A control circuit for controlling the rotational speed of a fan may include a memory element to store operating data corresponding to an operational profile of the fan defined by RPM (revolutions per minute) versus temperature, with the operating data comprising a respective temperature value and a respective RPM value for each respective operating point representing a change in slope of a function that corresponds to the operational profile of the fan. A processing unit may operate to receive a present temperature value, retrieve the operating data from the storage unit, and identify a pair of consecutive operating points such that the present temperature value is greater than a lower respective temperature value of the pair of consecutive operating points, and lower than a higher respective temperature value of the pair of consecutive operating points. The processing unit may calculate a desired RPM value corresponding to the present temperature value by performing linear interpolation between the pair of consecutive operating points, and output the desired RPM value to a closed-loop fan controller configured to control a rotational speed of the fan according at least to the desired RPM value.

Abstract translation: 用于控制风扇的转速的控制电路可以包括存储元件，用于存储与由RPM（每分钟转数）相对于温度定义的风扇的操作分布相对应的操作数据，其中操作数据包括相应的温度值和 每个相应的工作点的相应的RPM值表示与风扇的操作轮廓对应的功能的斜率的变化。 处理单元可以操作以接收当前温度值，从存储单元检索操作数据，并且识别一对连续的操作点，使得当前温度值大于该对连续工作点的较低相应温度值 ，并且低于该对连续工作点的相应温度值的较高值。 处理单元可以通过在一对连续的操作点之间进行线性插值来计算与当前温度值对应的期望的RPM值，并将期望的RPM值输出到闭环风扇控制器，该闭环风扇控制器被配置为根据 至少达到所需的RPM值。

公开(公告)号：US08239603B2

公开(公告)日：2012-08-07

申请号：US11417391

申请日：2006-05-03

Applicant: Drew J. Dutton ,  Alan D. Berenbaum ,  Raphael Weiss

Inventor： Drew J. Dutton ,  Alan D. Berenbaum ,  Raphael Weiss

IPC: G06F13/40

CPC classification number: G06F13/4027

Abstract: A system including a serialized secondary bus architecture. The system may include an LPC bus, an I/O controller, a serialized secondary bus, and at least one slave device. The LPC bus may be connected to the I/O controller, and the at least one slave device may be connected to the I/O controller via the serialized secondary bus. The serialized secondary bus has a reduced pin count relative to the LPC bus. The I/O controller may receive bus transactions from the LPC bus. The I/O controller may translate and forward LPC bus transactions to the at least one device over the secondary bus. The I/O controller may include a processing unit. The processing unit may initiate bus transactions intended for the at least one slave device. The I/O controller may also include a bus arbitration unit. The bus arbitration unit may arbitrate ownership of the secondary bus between the processing unit and the LPC bus.

Abstract translation: 一种包括序列化二次总线架构的系统。 该系统可以包括LPC总线，I / O控制器，串行化辅助总线和至少一个从设备。 LPC总线可以连接到I / O控制器，并且至少一个从设备可以经由串行辅助总线连接到I / O控制器。 串行次级总线相对于LPC总线的引脚数量减少。 I / O控制器可以从LPC总线接收总线事务。 I / O控制器可以通过辅助总线将LPC总线事务转换和转发到至少一个设备。 I / O控制器可以包括处理单元。 处理单元可以启动用于至少一个从设备的总线事务。 I / O控制器还可以包括总线仲裁单元。 总线仲裁单元可以仲裁处理单元和LPC总线之间的辅助总线的所有权。

公开(公告)号：US20120179847A1

公开(公告)日：2012-07-12

申请号：US13004890

申请日：2011-01-12

Applicant: ALAN BERENBAUM

Inventor： ALAN BERENBAUM

IPC: G06F13/36

CPC classification number: G06F13/4208

Abstract: The present disclosure describes a system and method for implementing bus operations with precise timing. The system includes a trigger descriptor register for a bus operation. The trigger descriptor register includes a bus definition field, which further includes data and address fields for providing data and address information for the bus operation. The trigger descriptor register may also include a holdoff time field to store a time value and includes an event select field to select a trigger for the bus operation. A processor configures the trigger descriptor register. A counter may count based on a time period such that at the end of the counting, the bus operation is performed based on the data and address fields. The time period is derived from one or more of the holdoff field or an external timer. The disclosed method and system employ hardware assist for maintaining precise timing while performing bus operations.

Abstract translation: 本公开描述了一种用于以精确的定时实现总线操作的系统和方法。 该系统包括用于总线操作的触发器描述符寄存器。 触发描述符寄存器包括总线定义字段，其还包括用于为总线操作提供数据和地址信息的数据和地址字段。 触发描述符寄存器还可以包括用于存储时间值的保留时间字段，并且包括事件选择字段以选择用于总线操作的触发。 处理器配置触发器描述符寄存器。 计数器可以基于时间段进行计数，使得在计数结束时，基于数据和地址字段执行总线操作。 该时间段从一个或多个保留字段或外部定时器导出。 所公开的方法和系统在执行总线操作时采用硬件辅助来维持精确定时。

公开(公告)号：US08190796B2

公开(公告)日：2012-05-29

申请号：US10979924

申请日：2004-11-02

Applicant: Neil Winchester ,  William Chiechi ,  Paul Brant

Inventor： Neil Winchester ,  William Chiechi ,  Paul Brant

IPC: G06F13/12 ,  G06F13/38 ,  G06F15/16

CPC classification number: G06F13/28

Abstract: A memory alignment system for efficient data transfer between a local memory that is configured in a host system, and a remote memory, comprises a data communications controller configured in the host system to align transmitted and received data based on formatting information received from the host system. When transmitting data from local system memory, for example over an Ethernet connection, communications control driver software may first write formatting information corresponding to the data into the data communications controller. The data communications controller is operable to align the data based on the formatting information as the driver software moves the data into a configurable transmit data buffer inside the data communications controller. Similarly, the driver software may write formatting information for receive data into a receive-format configuration buffer. The data communications controller may align the receive data based on the receive-formatting information as the receive data is being read by the host system. Because the data communications controller performs all the required data alignment, no data alignment by the host processor is required.

Abstract translation: 用于在配置在主机系统中的本地存储器与远程存储器之间进行有效数据传输的存储器对准系统包括配置在主机系统中的数据通信控制器，用于根据从主机系统接收的格式化信息对准发送和接收的数据 。 当从本地系统存储器发送数据时，例如通过以太网连接，通信控制驱动器软件可以首先将对应于数据的格式化信息写入数据通信控制器。 当驱动器软件将数据移动到数据通信控制器内的可配置发送数据缓冲器中时，数据通信控制器可操作以基于格式化信息对准数据。 类似地，驱动软件可以将用于接收数据的格式化信息写入接收格式配置缓冲器。 当主机系统正在读取接收数据时，数据通信控制器可以基于接收格式化信息对准接收数据。 由于数据通信控制器执行所有必需的数据对齐，因此不需要主机处理器进行数据对齐。

公开(公告)号：US07991943B2

公开(公告)日：2011-08-02

申请号：US11924826

申请日：2007-10-26

Applicant: Alan D. Berenbaum ,  Richard E. Wahler ,  Raphael Weiss

Inventor： Alan D. Berenbaum ,  Richard E. Wahler ,  Raphael Weiss

IPC: G06F12/02

CPC classification number: G06F12/1433 ,  G06F2212/2022

Abstract: System and method for implementing one time programmable (OTP) memory using embedded flash memory. A system-on-chip (SoC) includes a cleared flash memory array that includes an OTP block, including an OTP write inhibit field that is initially deasserted, a flash memory controller, and a controller. Data are written to the OTP block, including setting the OTP write inhibit field to signify prohibition of subsequent writes to the OTP block. The SoC is power cycled, and, in response, at least a portion of the OTP block is latched in a volatile memory, including asserting an OTP write inhibit bit based on the OTP write inhibit field, after which the OTP block is not writeable. In response to each subsequent power cycling, the controller is held in reset, the latching is performed, the controller is released from reset, and the flash array, now write protected, is configured to be controlled by the controller.

Abstract translation: 使用嵌入式闪存实现一次可编程（OTP）存储器的系统和方法。 片上系统（SoC）包括一个清除的闪存阵列，其中包括一个OTP块，包括一个最初被禁止的OTP写禁止字段，一个闪存控制器和一个控制器。 数据被写入OTP块，包括设置OTP写禁止字段以表示禁止对OTP块的后续写操作。 SoC是电源循环，并且作为响应，OTP块的至少一部分被锁存在易失性存储器中，包括基于OTP写禁止字段来断言OTP写禁止位，之后OTP块不可写。 响应于每次随后的电力循环，控制器保持复位，执行锁存，控制器从复位释放，并且现在写保护的闪存阵列被配置为由控制器控制。

公开(公告)号：US07990182B2

公开(公告)日：2011-08-02

申请号：US12050223

申请日：2008-03-18

Applicant: Scott C. McLeod

Inventor： Scott C. McLeod

IPC: H03K5/153

CPC classification number: H03F3/3076 ,  H03F3/45

Abstract: A low-current differential signal activity detector circuit may be configured to reject large common mode signals on differential input lines, while still detecting smaller differential signals applied to the same set of differential input lines. The detector circuit may comprise a translinear buffer that is driven at the buffer input and at the buffer output by the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be half-wave rectified through the buffer output devices and may be filtered to provide the detected output. When applying a common mode signal, the buffer's input and output may track each other, and no current may be rectified in the output devices, thus providing common-mode signal rejection. The detector circuit may also be configured with two buffers having their outputs coupled to a common node, each buffer input driven by a respective one of the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be fully rectified through the output devices of the two buffers, and may be filtered to provide the detected output. The two buffers may be configured in a symmetrical structure that allows for the rejection of common-mode signals when the outputs of the buffers are coupled to a common node.

Abstract translation: 低电流差分信号活动检测器电路可以被配置为在差分输入线上抑制大的共模信号，同时仍然检测到施加到同一组差分输入线的较小的差分信号。 检测器电路可以包括在缓冲器输入处被驱动并且通过差分输入信号在缓冲器输出处被驱动的跨线性缓冲器。 因此驱动检测器电路的输入的差分信号可以通过缓冲器输出装置进行半波整流，并且可以被滤波以提供检测的输出。 当应用共模信号时，缓冲器的输入和输出可以彼此跟踪，并且在输出设备中不会纠正电流，从而提供共模信号抑制。 检测器电路还可以配置有两个缓冲器，其具有耦合到公共节点的输出，每个缓冲器输入由差分输入信号中的相应一个驱动。 由此驱动检测器电路的输入的差分信号可以通过两个缓冲器的输出装置完全整流，并且可以被滤波以提供检测到的输出。 两个缓冲器可以配置成对称结构，当缓冲器的输出耦合到公共节点时允许抑制共模信号。

公开(公告)号：US07906994B2

公开(公告)日：2011-03-15

申请号：US12391414

申请日：2009-02-24

Applicant: Marshall J. Bell

Inventor： Marshall J. Bell

IPC: H03K3/00

CPC classification number: H03F3/45179 ,  H03F3/45654 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/78 ,  H03F2203/45008 ,  H03F2203/45074 ,  H03F2203/45292 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45631 ,  H04L25/0276

Abstract: A system and method for a fast stabilizing output buffer. A differential driver circuit is provided with an amplifier stage for receiving a differential input signal and generating a differential output based upon the input signal. The differential output has a corresponding common-mode (CM) voltage level typically based upon a value half of the power supply. A common-mode feedback buffer (CMFB) stage detects a change in the CM voltage level and recovers the CM voltage level to its desired value within a very fast settling time based upon a very high bus frequency. The CMFB stage utilizes a topology comprising only a single device. In one embodiment, this single device is a nmos transistor utilized as a transimpedance stage. Stability is provided by a circuit biasing stage and a shunting capacitor within the CMFB stage.

Abstract translation: 用于快速稳定输出缓冲器的系统和方法。 差分驱动器电路具有用于接收差分输入信号并基于输入信号产生差分输出的放大器级。 差分输出具有通常基于电源的一半值的对应的共模（CM）电压电平。 共模反馈缓冲器（CMFB）级检测CM电压电平的变化，并且基于非常高的总线频率在非常快的建立时间内将CM电压电平恢复到其期望值。 CMFB阶段使用仅包含单个设备的拓扑。 在一个实施例中，该单个器件是用作跨阻抗级的nmos晶体管。 稳定性由CMFB级内的电路偏置级和分流电容提供。