公开(公告)号：US20250022814A1

公开(公告)日：2025-01-16

申请号：US18898492

申请日：2024-09-26

Applicant: Intel Corporation

Inventor： William J. LAMBERT ,  Sri Chaitra Jyotsna CHAVALI

IPC: H01L23/64 ,  H01F27/28 ,  H01F27/32 ,  H01F41/04 ,  H01F41/12 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments include inductors and methods to form the inductors. An inductor includes a substrate layer that surrounds a magnetic layer, where the magnetic layer is embedded between the substrate layer. The inductor also includes a dielectric layer that surrounds the substrate and magnetic layers, where the dielectric layer fully embeds the substrate and magnetic layers. The inductor further includes a first conductive layer over the dielectric layer, a second conductive layer below the dielectric layer, and a plurality of plated-through-hole (PTH) vias in the dielectric and substrate layers. The PTH vias vertically extend from the first conductive layer to the second conductive layer, and the magnetic layer in between the PTH vias. The magnetic layer may have a thickness that is substantially equal to a thickness of the substrate layer, where the thickness of the magnetic layer is less than a thickness defined between the first and second conductive layers.

公开(公告)号：US20250022527A1

公开(公告)日：2025-01-16

申请号：US18902009

申请日：2024-09-30

Applicant: Intel Corporation

Inventor： Santhosh Kumar Chandrakanthan

IPC: G11C29/12 ,  G11C29/36

Abstract: An example integrated circuit disclosed herein includes a first die including first microbumps associated with a source-synchronous data interface of a three-dimensional (3D) die stack, a first one of the first microbumps in circuit with a clock output of the first die, a second one of the first microbumps in circuit with a data output of the first die, the clock output and the data output associated with a transmitter side of the source-synchronous data interface. The example integrated circuit also includes a second die including second microbumps associated with the source-synchronous data interface of the 3D die stack, a first one of the second microbumps in circuit with a clock input of the second die, a second one of the second microbumps in circuit with a data input of the second die, the clock input and the data input associated with a receiver side of the source-synchronous data interface.

公开(公告)号：US12200732B2

公开(公告)日：2025-01-14

申请号：US18374423

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Debdeep Chatterjee ,  Fatemeh Hamidi-Sepehr ,  Toufiqul Islam ,  Sergey Panteleev

IPC: H04W72/23 ,  H04L1/1812 ,  H04L5/00 ,  H04W8/24 ,  H04W72/566

Abstract: Systems for providing prioritization of UL transmissions in a UE are described. The prioritization information is used to resolve resource conflicts among UL transmissions that include conflicts between high priority UL transmissions, between an aperiodic-channel state information transmission and a scheduling request, and between a low priority UL transmission and a high priority UL transmission when timeline conditions for multiplexing in a single UL transmission are not met. The prioritization is based on timing and priority of the UL transmissions to determine which of the UL transmissions to transmit and which to cancel. Additional prioritization is based on reception by the UE of a cancelation index or in an additional overlapping high priority UL grant received in a DCI of a PDCCH that overlaps with at least one other PDCCH associated with the UL transmissions.

公开(公告)号：US12200663B2

公开(公告)日：2025-01-14

申请号：US18474805

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Alexandre Saso Stojanovski

IPC: H04W68/00 ,  H04W8/08 ,  H04W28/02 ,  H04W48/16 ,  H04W76/27

Abstract: The present disclosure describes techniques for utilizing paging cause values for paging user equipment (UE). The Paging Cause may be used for the UE in an CM_IDLE state or when the UE is in an RRC_INACTIVE state. A paging cause information element is included in a paging message, and includes a paging cause value. The paging cause value indicates a type of traffic that has initiated a paging operation. Other embodiments may be described and/or claimed.

公开(公告)号：US12200121B2

公开(公告)日：2025-01-14

申请号：US18477341

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Po-Kai Huang ,  Cheng Chen ,  Ido Ouzieli ,  Avner Epstein ,  Danny Alexander ,  Ofer Schreiber ,  Arik Klein ,  Daniel Bravo ,  Laurent Cariou ,  Ofer Hareuveni ,  Ehud Reshef ,  Nir Balaban

IPC: H04L9/08 ,  H04L61/5069 ,  H04L101/622 ,  H04W76/15

Abstract: This disclosure describes systems, methods, and devices related to security for multi-link operations. A multi-link device (MLD) may establish a first communication link between a first device of the MLD and a first device of a second MLD, and a second communication link between a second device of the MLD and a second device of the second MLD. The MLD may generate a group-addressed message. The MLD may protect the group-addressed message using a first key or a first integrity key. The MLD may protect the group-addressed message using a second key or a second integrity key. The MLD may send, using the first communication link, the group-addressed message protected using the first key or the first integrity key, and may send, using the second communication link, the group-addressed message protected using the second key or the second integrity key.

公开(公告)号：US12199168B2

公开(公告)日：2025-01-14

申请号：US17849198

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Andrew W. Yeoh ,  Ilsup Jin ,  Angelo Kandas ,  Michael L Hattendorf ,  Christopher P. Auth

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H01L49/02 ,  H10B10/00 ,  H01L23/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

公开(公告)号：US12199098B2

公开(公告)日：2025-01-14

申请号：US17211745

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Cory Weber ,  Stephen M. Cea ,  Leonard C. Pipes ,  Seahee Hwangbo ,  Rishabh Mehandru ,  Patrick Keys ,  Jack Yaung ,  Tzu-Min Ou

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/78

Abstract: Fin doping, and integrated circuit structures resulting therefrom, are described. In an example, an integrated circuit structure includes a semiconductor fin. A lower portion of the semiconductor fin includes a region having both N-type dopants and P-type dopants with a net excess of the P-type dopants of at least 2E18 atoms/cm3. A gate stack is over and conformal with an upper portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US12199085B2

公开(公告)日：2025-01-14

申请号：US17716934

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  Sairam Agraharam ,  Shengquan Ou ,  Thomas J De Bonis ,  Todd Spencer ,  Yang Sun ,  Guotao Wang

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/18

Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.

公开(公告)号：US12199063B2

公开(公告)日：2025-01-14

申请号：US18403545

申请日：2024-01-03

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Arun Chandrasekhar

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

公开(公告)号：US12198535B2

公开(公告)日：2025-01-14

申请号：US17955384

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： N. V. S. Kumar Srighakollapu ,  Ankur Mishra ,  Sreejith Satheesakurup ,  Saunak Bhalsod

IPC: G06F1/32 ,  G06F1/3212 ,  G06F3/02 ,  G08B5/36

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that implement an off-screen indication of battery charge in mobile platforms. In an example, the apparatus includes a keyboard, an interface circuitry, and a processor circuitry. The example processor circuitry to instantiate remaining state of charge (RSOC) controller circuitry to detect a battery charge level display event on a mobile device, the mobile device in a pre-boot state. The example processor circuitry additionally to instantiate fuel gauge circuitry to determine a charge level of a battery of the mobile device and keyboard display circuitry to, after the battery charge level display event, cause a display of the charge level of the battery in the pre-boot state with ones of backlights of a second ones keys on the keyboard.