公开(公告)号：US20030082873A1

公开(公告)日：2003-05-01

申请号：US10263361

申请日：2002-10-01

Applicant: STMicroelectronics S.r.I.

Inventor： Raffaele Zambrano

IPC: H01L021/8234

CPC classification number: H01L27/11502 ,  H01L21/76801 ,  H01L21/76837 ,  H01L21/76877 ,  H01L27/0629 ,  H01L27/1085 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

Abstract: A contact structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element where the contact is provided at an opening formed in an insulating layer which overlies at least in part the semiconductor layer. Further, the opening has its surface edges, walls and bottom coated with a metal layer and filled with an insulating layer.

公开(公告)号：US20030064558A1

公开(公告)日：2003-04-03

申请号：US10225315

申请日：2002-08-20

Applicant: STMicroelectronics S.r.I.

Inventor： Alessandro Grossi ,  Cesare Clementi

IPC: H01L021/8238

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11536

Abstract: A process for the manufacturing of electronic devices, including memory cells, involving forming, on a substrate of semiconductor material, multilayer stacks including a floating gate region, an intermediate dielectric region, and a control gate region; forming a protective layer extending on top of the substrate and between the multilayer stacks and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks includes the step of defining the control gate region on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer isolates the multilayer stacks from each other at the sides. Word lines of metal extend above the protective layer and are in electrical contact with the gate regions.

公开(公告)号：US20030059046A1

公开(公告)日：2003-03-27

申请号：US10199965

申请日：2002-07-18

Applicant: STMicroelectronics S.r.I.

Inventor： Marco Messina ,  Salvatore Polizzi ,  Giulio Mangione

IPC: H04L009/00

CPC classification number: H04L9/0662 ,  H04L2209/12 ,  H04L2209/26

Abstract: A hybrid architecture for realizing a random numbers generator comprising a digital circuitry portion able to provide for a random bytes sequence as well as an analog circuitry portion able to provide a seed of the true random type is described.

Abstract translation: 描述了用于实现随机数生成器的混合架构，其包括能够提供随机字节序列的数字电路部分以及能够提供真随机类型的种子的模拟电路部分。

公开(公告)号：US20030058024A1

公开(公告)日：2003-03-27

申请号：US10216562

申请日：2002-08-09

Applicant: STMicroelectronics S.r.I.

Inventor： Maurizio Zuffada ,  Giorgio Betti ,  Francesco Chrappan Soldavini ,  Martin Aureliano Hassner

IPC: G06F001/00

CPC classification number: H03H11/481

Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as a capacitor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.

Abstract translation: 集成电子电路包括级联连接在一起的多个有源电路。 反馈回路在最后一个有效电路的输出和第一有源电路的输入之间，使得多个有源器件用作诸如电容器之类的非线性器件。 集成电子电路可以与包括其他非线性装置的电路网络相关联地集成或使用。

公开(公告)号：US20030026596A1

公开(公告)日：2003-02-06

申请号：US10177729

申请日：2002-06-20

Applicant: STMicroelectronics S.r.I.

Inventor： Giorgio Betti ,  Angelo Dati ,  Viviana D'Alto ,  Danilo Pau ,  Filippo Santinello

IPC: H03M013/00 ,  H04N007/26

CPC classification number: H04N19/00266 ,  H04N19/157 ,  H04N19/172 ,  H04N19/61

Abstract: A method of storing a data file, particularly in the MPEG format and including a flow of different frames, comprises a protection system for the data file based on a parameter stored in the data file. Advantageously, the storage method comprises selectively protecting the frames by storing parameters that are associated with corresponding different frames whose values are selected to provide a playing quality level requested by an end user. Also, a method is provided for decoding a data file, particularly of the MPEG type and including a flow of different frames, wherein the data file is stored per above.

Abstract translation: 特别是以MPEG格式存储并包括不同帧流的数据文件的方法包括基于存储在数据文件中的参数的数据文件的保护系统。 有利地，存储方法包括通过存储与其值被选择的相应不同帧相关联的参数来选择性地保护帧，以提供终端用户请求的播放质量等级。 此外，提供了一种用于对数据文件进行解码的方法，特别是MPEG类型的数据文件，并且包括不同帧的流程，其中数据文件存储在上面。

公开(公告)号：US20030012303A1

公开(公告)日：2003-01-16

申请号：US10159773

申请日：2002-05-31

Applicant: STMicroelectronics S.r.I.

Inventor： Angelo Dati ,  Cecilia Tonci ,  Paolo Gaducci

IPC: H04L027/22 ,  H04L027/14 ,  H04L027/06

CPC classification number: G11B20/10009

Abstract: A method is provided for optimizing a PRML (Partial Response Maximum Likelihood) receiving channel for mass memory data receiving systems comprising an input receiving channel, a receiver placed downstream of the channel, a detector connected in cascade to the receiver, and a summing node being input both the receiver output through a delay line, and the output from the detector through an impulsive filter. The method includes performing an indirect estimate of the noise strength by filtering out the error sequence, i.e. the output signal from the summing node, through a filter, and selecting either the output from the summing node or the output from the filter to obtain an optimization parameter for feedback to the receiving system.

Abstract translation: 提供一种用于优化用于大容量存储器数据接收系统的PRML（部分响应最大似然）接收通道的方法，所述接收通道包括输入接收通道，放置在通道下游的接收器，级联连接到接收器的检测器， 通过延迟线输入接收器输出，并通过脉冲滤波器输入来自检测器的输出。 该方法包括通过滤除误差序列，即来自求和节点的输出信号，通过滤波器，以及选择来自求和节点的输出或来自滤波器的输出来获得最优化来执行噪声强度的间接估计 用于反馈给接收系统的参数。

公开(公告)号：US20030012064A1

公开(公告)日：2003-01-16

申请号：US10176387

申请日：2002-06-20

Applicant: STMICROELECTRONICS S.r.I.

Inventor： Franco Enrico Beretta

IPC: G11C029/00

CPC classification number: G11C16/3431 ,  G11C16/3418

Abstract: A method (1110a;1110b) of refreshing an electrically erasable and programmable non-volatile memory (100) having a plurality of memory cells (Mhk) is proposed. The method includes the steps of: verifying (1106-1114; 1152-1162) whether a memory cell has drifted from a correct condition (i.e., a predetermined voltage and/or voltage range), and individually restoring (1116-1130) the correct condition of the memory cell if the result of the verification is positive.

Abstract translation: 提出了刷新具有多个存储单元（Mhk）的电可擦除可编程非易失性存储器（100）的方法（1110a; 1110b）。 该方法包括以下步骤：验证（1106-1114; 1152-1162）存储器单元是否已经从正确的状态漂移（即，预定的电压和/或电压范围），并且单独地恢复（1116-1130）正确的 验证结果为正的存储单元条件。

公开(公告)号：US20020190675A1

公开(公告)日：2002-12-19

申请号：US10175451

申请日：2002-06-18

Applicant: STMICROELECTRONICS S.r.I

Inventor： Michele Boscolo

IPC: H02P001/18

CPC classification number: H02P6/14

Abstract: The present invention relates to a method and a circuit using the method thereof for minimising the phase errors during the driving of an electric motor, and a circuit using the method thereof, having a stator winding, a permanent magnet rotor assembly, and devices able to sense a rotor position, which comprises the following steps: a) generating of a rotor position signal (10, 14, 39), by means of said devices able to sense said rotor position; b) detecting at least two information from at least two edges (11, 12; 15, 16) of said rotor position signal (10, 14, 39) inside a measure period; c) generating a driving signal (9, 13, 38), in finction of said at least two information (11, 12; 15, 16) inside the measure period, so as to follow the rotor velocity.

Abstract translation: 本发明涉及使用该方法和方法来最小化电动机驱动期间的相位误差的方法和电路，以及使用该方法的电路，其具有定子绕组，永磁转子组件和能够 感测转子位置，其包括以下步骤：a）通过能够感测所述转子位置的所述装置产生转子位置信号（10,14,39）; b）在测量周期内从所述转子位置信号（10,14,39）的至少两个边缘（11,12; 15,16）检测至少两个信息; c）在所述测量周期内的所述至少两个信息（11,12; 15,16）中产生驱动信号（9,13,38），以便跟随转子速度。

公开(公告)号：US20020184420A1

公开(公告)日：2002-12-05

申请号：US10115888

申请日：2002-04-03

Applicant: STMicroelectronics S.r.I.

Inventor： Alessandro Francesco Maone ,  Maurizio Francesco Perroni

IPC: G06F013/42

CPC classification number: G06F13/4239

Abstract: An interface manages the exchange of information between a bus system and a memory during reading, according to a communication protocol. The interface has a protocol-decoding unit, which receives from outside commands and information for managing the reading and generates a wait-code enabling signal, and a wait-state generating unit, which is connected to the protocol-decoding unit and outputs wait codes upon receipt of the wait-code enabling signal. When the memory ends reading, as signaled by switching of a read-state signal, a wait-state disabling circuit generates and supplies an end-of-waiting control signal to the wait-state generating unit, which thus outputs an end-of-waiting code.

Abstract translation: 根据通信协议，接口在读取期间管理总线系统和存储器之间的信息交换。 该接口具有从外部指令接收的协议解码单元和用于管理读取的信息并产生等待代码使能信号，以及等待状态生成单元，其连接到协议解码单元并输出等待代码 在接收到等待代码使能信号时。 当存储器结束读取时，如通过切换读取状态信号所指示的，等待状态禁止电路产生并将等待结束的控制信号提供给等待状态产生单元，从而输出结束等待状态， 等待代码。

公开(公告)号：US20020145909A1

公开(公告)日：2002-10-10

申请号：US10077687

申请日：2002-02-15

Applicant: STMicroelectronics S.r.I.

Inventor： Alessandro Francesco Maone ,  Maurizio Francesco Perroni

IPC: G11C011/34

CPC classification number: G11C16/32 ,  G11C16/26

Abstract: The reading timing device has a data-sensing stage, receiving a sensing-latch signal, and an output stage, including an output buffer and enabled at a first switching edge of a synchronization signal. A reading timing stage generates the sensing-latch signal not before a preset time interval from the first switching edge of the synchronization signal. Thereby, reading, in particular data-latching in the data-sensing stage, is temporarily separated from switching of the output buffers. This separation is obtained using the sync signal. Since the output buffers must switch in a preset time from the rising edge of the sync signal, the pulse of the sensing-latch signal is shifted after this time, and more precisely after the falling edge of the sync signal.

Abstract translation: 读取定时装置具有数据感测级，接收感测锁存信号，以及输出级，包括输出缓冲器，并在同步信号的第一开关边沿使能。 读取定时阶段不是在从同步信号的第一切换边缘的预设时间间隔之前产生感测锁存信号。 因此，读取，特别是数据传感级中的数据锁存，暂时与输出缓冲器的切换分开。 使用同步信号获得该分离。 由于输出缓冲器必须在同步信号的上升沿的预设时间内切换，所以在此时间之后，更精确地在同步信号的下降沿之后移动感测锁存信号的脉冲。