Closed-loop position control of MEMS micromirrors

    公开(公告)号:US11841497B2

    公开(公告)日:2023-12-12

    申请号:US17109929

    申请日:2020-12-02

    CPC classification number: G02B26/0833 G05B5/01 G09G3/025 H03G1/0005 H04N9/3135

    Abstract: Disclosed herein is a control system for a projection system, including a first subtractor receiving an input drive signal and a feedback signal and generating a first difference signal therefrom, the feedback signal being indicative of position of a quasi static micromirror of the projection system. A type-2 compensator receives the first difference signal and generates therefrom a first output signal. A derivative based controller receives the feedback signal and generates therefrom a second output signal. A second subtractor receives the first and second output signals and generates a second difference signal therefrom. The second difference signal serves to control a mirror driver of the projection system. A higher order resonance equalization circuit receives a pre-output signal from an analog front end of the projection system that is indicative of position of the quasi static micromirror, and generates the feedback signal therefrom.

    SENSOR DEVICE AND RELATED METHOD AND SYSTEM
    132.
    发明公开

    公开(公告)号:US20230396407A1

    公开(公告)日:2023-12-07

    申请号:US18453018

    申请日:2023-08-21

    CPC classification number: H04L7/0079

    Abstract: A sensor includes detection circuitry and control circuitry coupled to the detection circuitry. The detection circuitry generates a detection signal indicative of a detected physical quantity. The control circuitry, in operation receives the detection signal and a frequency-indication signal, and generates a trigger signal based on the frequency-indication signal and a set of local reference signals. The sensor generates a digital output signal and a locking signal based on the trigger signal and the detection signal. The generating the digital output signal includes outputting a sample of the digital output signal based on the trigger signal. The locking signal is temporally aligned with the digital output signal.

    CIRCUIT ARRANGEMENT FOR VALIDATION OF OPERATION OF A LOGIC MODULE IN A MULTIPOWER LOGIC ARCHITECTURE AND CORRESPONDING VALIDATION METHOD

    公开(公告)号:US20230393198A1

    公开(公告)日:2023-12-07

    申请号:US18324583

    申请日:2023-05-26

    CPC classification number: G01R31/3177 G06F1/08 G01R31/31725

    Abstract: A first circuit is coupled to a second circuit via a communication link. The first circuit generates a first validation signal, a second validation signal, and control signals, and transmits the first and second validation signals to the second circuit via the communication link. The second circuit validates the control signals based on the first and second binary validation signals. The validating includes: verifying that when the first validation signal has a first value, the second validation signal has a second value different from the first value; verifying that when the second validation signal has the first value, the first validation signal has the second value; verifying detection of a transition edge of the first validation signal within a threshold number of clock cycles; and verifying detection of a transition edge of the second validation signal within the threshold number of clock cycles.

    LID ANGLE DETECTION
    136.
    发明公开
    LID ANGLE DETECTION 审中-公开

    公开(公告)号:US20230384837A1

    公开(公告)日:2023-11-30

    申请号:US18183464

    申请日:2023-03-14

    CPC classification number: G06F1/1677 H04M1/0245 G06F1/3246 G01C1/00 G01C9/08

    Abstract: The present disclosure is directed to a device and method for lid angle detection that is accurate even if the device is activated in an upright position. While the device is in a sleep state, first and second sensor units measure acceleration and angular velocity, and calculate orientations of respective lid components based on the acceleration and angular velocity measurements. Upon the device exiting the sleep state, a processor estimates the lid angle using the calculated orientations, sets the estimated lid angle as an initial lid angle, and updates the initial lid angle using, for example, two accelerometers; two accelerometers and two gyroscopes; two accelerometers and two magnetometers; or two accelerometers, two gyroscopes, and two magnetometers.

    DYNAMIC CURRENT SCALING OF A REGULATOR
    138.
    发明公开

    公开(公告)号:US20230367342A1

    公开(公告)日:2023-11-16

    申请号:US17741994

    申请日:2022-05-11

    CPC classification number: G05F1/10

    Abstract: A method and apparatus for performing dynamic current scaling of an input current of a voltage regulator are provided. The method and apparatus allow tuning current consumption in various applications, calculating a duration of an activity phase in which various algorithms are executed and activating dynamic current scaling of a regulator if the activity duration is shorter than a programmable threshold. A controller receives a threshold for an activity duration and a window size in which to evaluate the activity duration.

    CIRCUIT HAVING AN AMPLIFIER STAGE AND A CURRENT MIRROR LOOP OR STABILITY NETWORK

    公开(公告)号:US20230361737A1

    公开(公告)日:2023-11-09

    申请号:US18303931

    申请日:2023-04-20

    CPC classification number: H03F3/45475 H03F3/45273 H03F1/483 H03F1/086

    Abstract: A circuit an amplifier stage that amplifier stage includes a positive amplifier branch and a negative amplifier branch and has current flow paths therethrough cascaded in a flow line for a core current for the amplifier stage between a supply node and a ground node. The positive and negative amplifier branches have respective input nodes configured to receive an input signal applied therebetween. A current mirror loop can be coupled to the respective input nodes of the positive and negative amplifier branches and provides an adjustable high-impedance bias source for the core current for the amplifier stage. In addition to, or instead of the current mirror loop, the circuit can include stability network having a gain bandwidth range. The amplifier stage is configured to short-circuit the output signal from the amplifier stage within the gain bandwidth range based on an output voltage setting signal.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE

    公开(公告)号:US20230361010A1

    公开(公告)日:2023-11-09

    申请号:US18140194

    申请日:2023-04-27

    Inventor: Riccardo VILLA

    Abstract: A semiconductor chip or die is arranged on a first surface of a thermally conductive die pad of a substrate such as a leadframe. An encapsulation of insulating material in molded onto the die pad having the semiconductor die arranged on the first surface. At the second surface of the die pad, opposite the first surface, the encapsulation borders on the die pad at a borderline around the die pad. A recessed portion of the encapsulation is provided, for example, via laser ablation, at the borderline around the die pad. Thermally conductive material such as metal material is filled in the recessed portion of the encapsulation around the die pad. The surface area of the thermally conductive die pad is augmented by the filling of thermally conductive material in the recessed portion of the encapsulation thus improving thermal performance of the device.

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