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    Use of band edge gate metals as source drain contacts
    131.
    发明授权
    Use of band edge gate metals as source drain contacts 有权
    使用带边栅极金属作为源极漏极触点

    公开(公告)号：US08741753B2

    公开(公告)日：2014-06-03

    申请号：US13611736

    申请日：2012-09-12

    Applicant: Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

    Inventor： Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

    IPC: H01L21/20 ,  H01L21/3205 ,  H01L21/00

    CPC classification number: H01L29/7833 ,  H01L21/28512 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

    Abstract: A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.

    Abstract translation: 一种器件包括形成在半导体衬底中的沟道上方的栅叠层。 栅极堆叠包括栅极绝缘体材料层，覆盖栅极绝缘体材料层的栅极金属层和覆盖层带边缘栅极金属的接触金属层。 该装置还包括邻近通道的源极和漏极接触。 源极和漏极触点各自包括覆盖并与半导体衬底的掺杂区域直接电接触的栅极金属层以及覆盖在栅极金属层上的接触金属层。

    MOSFET integrated circuit with uniformly thin silicide layer and methods for its manufacture
    133.
    发明授权
    MOSFET integrated circuit with uniformly thin silicide layer and methods for its manufacture 有权
    具有均匀薄的硅化物层的MOSFET集成电路及其制造方法

    公开(公告)号：US08652963B2

    公开(公告)日：2014-02-18

    申请号：US13237732

    申请日：2011-09-20

    Applicant: Bin Yang ,  Christian Lavoie ,  Emre Alptekin ,  Ahmet S. Ozcan ,  Cung D. Tran ,  Mark Raymond

    Inventor： Bin Yang ,  Christian Lavoie ,  Emre Alptekin ,  Ahmet S. Ozcan ,  Cung D. Tran ,  Mark Raymond

    IPC: H01L21/44

    CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L29/6659 ,  H01L29/7833

    Abstract: An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.

    Abstract translation: 提供具有均匀厚度的硅化物层的MOSFET器件及其制造方法。 一种这样的方法包括在硅半导体衬底的表面上的宽且窄的接触沟槽上沉积金属层。 在金属/硅界面处形成均匀薄的无定形混合合金层时，除去过量的（未反应的）金属。 该器件被退火以促进在衬底表面上形成薄的硅化物层，其在宽和窄接触沟槽的底部显示均匀的厚度。

    WATERMARKING IMAGE BLOCK DIVISION METHOD AND DEVICE FOR WESTERN LANGUAGE WATERMARKING PROCESSING
    134.
    发明申请
    WATERMARKING IMAGE BLOCK DIVISION METHOD AND DEVICE FOR WESTERN LANGUAGE WATERMARKING PROCESSING 有权
    WATERMARKING图像块分割方法和西语言水印处理装置

    公开(公告)号：US20140003649A1

    公开(公告)日：2014-01-02

    申请号：US13997258

    申请日：2011-12-23

    Applicant: Gaoyang Wang ,  Wenfa Qi ,  Lidong Wang ,  Bin Yang

    Inventor： Gaoyang Wang ,  Wenfa Qi ,  Lidong Wang ,  Bin Yang

    IPC: G06T1/00

    CPC classification number: G06T1/0021 ,  G06K9/348 ,  G06K2209/01 ,  G06T2201/0051 ,  G06T2201/0062 ,  G06T2201/0083

    Abstract: The application provides a method for partitioning a watermark image with western language characters, comprising: partitioning a western language characters image along rows and columns to form a plurality of character image blocks; identifying valid character image blocks from the formed character image blocks; counting sizes of the valid character image blocks to determine if the image corresponds to a document with a large font size or a document with a small font size; dividing words in the image into a plurality of groups, wherein each divided group in the document with large font size has different numbers of words from that with small font size; and dividing equally the divided word groups into multiple portions corresponding to watermark image blocks. The application further provides a device for partitioning a watermark image with western language characters. The operability of watermark embedding process can be ensured through the above technical solution.

    Abstract translation: 该应用程序提供了一种用于用西方语言字符分割水印图像的方法，包括：沿着行和列划分西方语言字符图像以形成多个字符图像块; 从形成的字符图像块中识别有效的字符图像块; 计算有效字符图像块的大小，以确定图像是否对应于具有较大字体大小的文档或具有小字体大小的文档; 将图像中的单词划分成多个组，其中具有大字体大小的文档中的每个划分组具有与具有小字体尺寸的单词不同的字数; 并将划分的字组分成相当于水印图像块的多个部分。 该应用还提供了一种用于用西语字符分割水印图像的设备。 通过上述技术方案可以确保水印嵌入过程的可操作性。

    ETSOI with reduced extension resistance
    135.
    发明授权
    ETSOI with reduced extension resistance 有权
    ETSOI具有降低的延伸电阻

    公开(公告)号：US08518758B2

    公开(公告)日：2013-08-27

    申请号：US12726889

    申请日：2010-03-18

    Applicant: Bin Yang ,  Man Fai Ng

    Inventor： Bin Yang ,  Man Fai Ng

    IPC: H01L27/12

    CPC classification number: H01L29/78618 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78684 ,  H01L29/78696

    Abstract: A semiconductor is formed on an SOI substrate, such as an extremely thin SOI (ETSOI) substrate, with increased extension thickness. Embodiments include semiconductor devices having an epitaxially formed silicon-containing layer, such as embedded silicon germanium (eSiGe), on the SOI substrate. An embodiment includes forming an SOI substrate, epitaxially forming a silicon-containing layer on the SOI substrate, and forming a gate electrode on the epitaxially formed silicon-containing layer. After gate spacers and source/drain regions are formed, the gate electrode and underlying silicon-containing layer are removed and replaced with a high-k metal gate. The use of an epitaxially formed silicon-containing layer reduces SOI thickness loss due to fabrication process erosion, thereby increasing extension thickness and lowering extension resistance.

    Abstract translation: 在诸如极薄的SOI（ETSOI）衬底的SOI衬底上形成半导体，具有增加的延伸厚度。 实施例包括在SOI衬底上具有外延形成的含硅层（例如嵌入硅锗（eSiGe））的半导体器件。 实施例包括形成SOI衬底，在SOI衬底上外延形成含硅层，并在外延形成的含硅层上形成栅电极。 在形成栅极间隔物和源极/漏极区之后，去除栅电极和下面的含硅层，并用高k金属栅极代替。 使用外延形成的含硅层由于制造工艺侵蚀而减少SOI厚度损失，从而增加延伸厚度并降低延伸电阻。

    Accelerometer
    137.
    发明授权
    Accelerometer 有权
    加速度计

    公开(公告)号：US08413511B2

    公开(公告)日：2013-04-09

    申请号：US13015987

    申请日：2011-01-28

    Applicant: Zhou Ge ,  Bin Yang ,  Zheng-Kui Meng ,  Yi-Lin Yan ,  Rui Zhang

    Inventor： Zhou Ge ,  Bin Yang ,  Zheng-Kui Meng ,  Yi-Lin Yan ,  Rui Zhang

    IPC: G01P15/125

    CPC classification number: G01P15/125 ,  G01P15/18 ,  G01P2015/082 ,  G01P2015/0848 ,  G01P2015/0854

    Abstract: A accelerometer includes a substrate define a stationary electrode thereon, a first moveable mass defining a conductive-layer thereon facing the stationary electrode, a plurality of first elastic elements coupled with a peripheral side of the first moveable mass, a first fixed element surrounding the first moveable mass and fixedly attached to the substrate, a plurality of first fixed electrodes extending outwardly from the first fixed element, a second moveable mass surrounding the first fixed electrodes, a plurality of first moveable electrodes extending inwardly from the second moveable mass toward the first fixed element and parallel to the first fixed electrodes, respectively, a plurality of second elastic elements coupled with a peripheral side of the second moveable mass, and a second fixed element surrounding the second moveable mass and fixedly attached to the substrate.

    Abstract translation: 加速度计包括在其上限定固定电极的基板，限定其面向固定电极的导电层的第一可移动质量块，与第一可移动质量块的周边连接的多个第一弹性元件，围绕第一 可移动的质量并且固定地附接到基板，从第一固定元件向外延伸的多个第一固定电极，围绕第一固定电极的第二可移动质量;从第二可移动质量向内朝向第一固定 并且与第一固定电极平行的多个第二弹性元件分别与第二可移动质量体的周边连接，第二固定元件围绕第二可移动质量块并且固定地附着在基底上。

    Metal-semiconductor intermixed regions
    139.
    发明授权
    Metal-semiconductor intermixed regions 有权
    金属半导体混合区域

    公开(公告)号：US08278200B2

    公开(公告)日：2012-10-02

    申请号：US13012043

    申请日：2011-01-24

    Applicant: Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

    Inventor： Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

    IPC: H01L21/20

    CPC classification number: H01L21/28518

    Abstract: In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.

    Abstract translation: 在一个示例性实施例中，一种可由机器读取的程序存储设备，其有形地体现了可由机器执行的用于执行操作的指令程序，所述操作包括：在半导体结构的表面上沉积具有第一金属的第一层， 第一层在第一层和半导体结构的界面处形成第一混合区; 去除沉积的第一层的一部分以暴露第一混合区; 在所述第一混合区域上沉积具有第二金属的第二层，其中沉积所述第二层在所述第二层和所述第一混合区的界面处产生第二混合区; 去除沉积的第二层的一部分以暴露第二混合区; 以及在所述半导体结构上执行至少一个退火。

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