公开(公告)号：US20090061547A1

公开(公告)日：2009-03-05

申请号：US12266443

申请日：2008-11-06

申请人： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

发明人： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

IPC分类号： H01L21/66

CPC分类号： H01L21/76895

摘要： A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.

摘要翻译： 用作与半导体器件中的结构相邻的导电间隔件的接触件的接合焊盘包括两个岛，每个岛基本上为矩形并且彼此间隔开并且与该结构隔开。 导电间隔件与每个岛相邻并且彼此重叠并与邻近结构的导电间隔物重叠。 与着陆垫的接触在邻近岛的导电间隔物上并且与结构间隔开。

公开(公告)号：US20090059660A1

公开(公告)日：2009-03-05

申请号：US11849992

申请日：2007-09-04

申请人： Dana Lee ,  Emilio Yero

发明人： Dana Lee ,  Emilio Yero

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

摘要翻译： 提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。 存储单元分为两个或更多个组。 在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。 在第一触发之前，第一组存储器单元与第二组存储器单元一起编程。 在第一触发之后和在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。 在第二触发之后，第一组存储器单元与第二组存储器单元一起被编程。 在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

公开(公告)号：US07433241B2

公开(公告)日：2008-10-07

申请号：US11618580

申请日：2006-12-29

申请人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee ,  Gerrit Jan Hemink

发明人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee ,  Gerrit Jan Hemink

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C7/1048 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427

摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at higher voltages for certain memory cells that may have undergone partial programming.

摘要翻译： 在编程期间，未选择的非易失性存储元件组被提升以减少或消除连接到所选字线的目标但未选择的存储器单元的程序干扰。 在将程序电压施加到所选择的字线并升高未选择的组之前，未选择的组被预先充电，以通过为未选择的组提供更大的增强电位来进一步减少或消除程序干扰。 在预充电期间，对于可能已经经过部分编程的某些存储器单元，在较高电压下提供一个或多个预充电使能信号。

公开(公告)号：US07227217B2

公开(公告)日：2007-06-05

申请号：US11078562

申请日：2005-02-28

申请人： Amitay Levi ,  Pavel Klinger ,  Bomy Chen ,  Hieu Van Tran ,  Dana Lee ,  Jack E. Frayer

发明人： Amitay Levi ,  Pavel Klinger ,  Bomy Chen ,  Hieu Van Tran ,  Dana Lee ,  Jack E. Frayer

IPC分类号： H01L29/788 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/7885

摘要： A nonvolatile memory cell having a floating gate for the storage of charges thereon has a control gate and a separate erase gate. The cell is programmed by hot channel electron injection and is erased by poly to poly Fowler-Nordheim tunneling. A method for making an array of unidirectional cells in a planar substrate, as well as an array of bidirectional cells in a substrate having a trench, is disclosed. An array of such cells and a method of making such an array is also disclosed.

摘要翻译： 具有用于存储电荷的浮动栅极的非易失性存储单元具有控制栅极和单独的擦除栅极。 该电池通过热通道电子注入进行编程，并被poly-poly Fowler-Nordheim隧道擦除。 公开了一种用于在平面基板中制造单向单元阵列的方法，以及在具有沟槽的基板中的双向单元阵列。 还公开了这样的单元阵列和制造这种阵列的方法。

公开(公告)号：US20060081945A1

公开(公告)日：2006-04-20

申请号：US11292557

申请日：2005-12-02

申请人： Dana Lee ,  Bomy Chen

发明人： Dana Lee ,  Bomy Chen

IPC分类号： H01L29/76

CPC分类号： H01L27/11266 ,  G11C11/5692 ,  G11C17/12 ,  H01L27/112

摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.

摘要翻译： 多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。 每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。 通道在第一和第二区域之间。 通道具有三个部分，第一部分，第二部分和第三部分。 门间隔开并与通道的至少第二部分绝缘。 每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻 第一区域和/或与第二区域相邻的通道的第三部分。 在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。 同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。 最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

公开(公告)号：US20060079053A1

公开(公告)日：2006-04-13

申请号：US10962008

申请日：2004-10-08

申请人： Bomy Chen ,  Dana Lee ,  Yaw Hu ,  Bing Yeh

发明人： Bomy Chen ,  Dana Lee ,  Yaw Hu ,  Bing Yeh

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28114 ,  H01L27/11568 ,  H01L29/66553

摘要： A method of forming a memory device (and the resulting device) by forming an electron trapping dielectric material over a substrate, forming conductive material over the dielectric material, forming a spacer of material over the conductive material, removing portions of the dielectric material and the conductive material to form segments thereof disposed underneath the spacer of material, forming first and second spaced-apart regions in the substrate having a second conductivity type different from that of the substrate, with a channel region extending between the first and second regions, with the segments of the dielectric and first conductive materials being disposed over a first portion of the channel region for controlling a conductivity thereof, and forming a second conductive material over and insulated from a second portion of the channel region for controlling a conductivity thereof.

摘要翻译： 一种通过在衬底上形成电子捕获电介质材料形成存储器件（和所得器件）的方法，在电介质材料上形成导电材料，在导电材料上形成材料间隔物，去除电介质材料的部分和 导电材料以形成位于材料间隔物下方的段，在衬底中形成具有不同于衬底的第二导电类型的第一和第二间隔开的区域，沟道区域在第一和第二区域之间延伸， 电介质和第一导电材料的片段设置在沟道区域的第一部分上，用于控制其导电率，并且在沟道区域的第二部分上形成第二导电材料并与之绝缘以控制其导电性。

公开(公告)号：US07012310B2

公开(公告)日：2006-03-14

申请号：US10642078

申请日：2003-08-14

申请人： Dana Lee ,  Bomy Chen

发明人： Dana Lee ,  Bomy Chen

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11266 ,  G11C11/5692 ,  G11C17/12 ,  H01L27/112

摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.

摘要翻译： 多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。 每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。 通道在第一和第二区域之间。 通道具有三个部分，第一部分，第二部分和第三部分。 门间隔开并与通道的至少第二部分绝缘。 每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻 第一区域和/或与第二区域相邻的通道的第三部分。 在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。 同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。 最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

公开(公告)号：US20060014339A1

公开(公告)日：2006-01-19

申请号：US11221161

申请日：2005-09-06

申请人： Dana Lee ,  Wen-Juei Lu ,  Felix Tsui

发明人： Dana Lee ,  Wen-Juei Lu ,  Felix Tsui

IPC分类号： H01L21/8238

CPC分类号： H01L21/76895

摘要： A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.

摘要翻译： 用作与半导体器件中的结构相邻的导电间隔件的接触件的接合焊盘包括两个岛，每个岛基本上为矩形并且彼此间隔开并且与该结构隔开。 导电间隔件与每个岛相邻并且彼此重叠并与邻近结构的导电间隔物重叠。 与着陆垫的接触在邻近岛的导电间隔物上并且与结构间隔开。

公开(公告)号：US20050237807A1

公开(公告)日：2005-10-27

申请号：US11111244

申请日：2005-04-20

申请人： Bomy Chen ,  Jack Frayer ,  Dana Lee

发明人： Bomy Chen ,  Jack Frayer ,  Dana Lee

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C16/0458 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7887

摘要： A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate.

摘要翻译： 双向读/写非易失性存储单元和阵列能够实现高密度。 每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。 电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。 浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。 控制栅极连接到每个源极/漏极区域，并且还电容耦合到浮动栅极。 通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。 双向读取允许将单元编程为存储位，每个浮动栅极中有一位。

公开(公告)号：US06958273B2

公开(公告)日：2005-10-25

申请号：US10394975

申请日：2003-03-21

申请人： Bomy Chen ,  Dana Lee

发明人： Bomy Chen ,  Dana Lee

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7885

摘要： A method of forming a floating gate memory cell array, and the array formed thereby, wherein a trench is formed into the surface of a semiconductor substrate. The source and drain regions are formed underneath the trench and along the substrate surface, respectively, with a non-linear channel region therebetween. The floating gate has a lower portion disposed in the trench and an upper portion disposed above the substrate surface and having a lateral protrusion extending parallel to the substrate surface. The lateral protrusion is formed by etching a cavity into an exposed end of a sacrificial layer and filling it with polysilicon. The control gate is formed about the lateral protrusion and is insulated therefrom. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge that points toward the floating gate and in a direction opposite to that of the lateral protrusion.

摘要翻译： 一种形成浮栅存储单元阵列的方法和由此形成的阵列，其中沟槽形成在半导体衬底的表面中。 源极和漏极区分别形成在沟槽下方并且沿着衬底表面，其间具有非线性沟道区。 浮动栅极具有设置在沟槽中的下部和设置在基板表面上方并具有平行于基板表面延伸的横向突起的上部。 横向突起通过将空腔蚀刻到牺牲层的暴露端并用多晶硅填充而形成。 控制门围绕横向突起形成并与其绝缘。 沟槽侧壁以锐角与衬底表面相接触以形成指向浮动栅极并且沿与横向突起的方向相反的方向的尖锐边缘。