公开(公告)号：US07687841B2

公开(公告)日：2010-03-30

申请号：US11195433

申请日：2005-08-02

申请人： Gurtej Sandhu

发明人： Gurtej Sandhu

IPC分类号： H01L27/108

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L51/0048 ,  H01L51/0541 ,  H01L51/055 ,  Y10S977/742

摘要： A structure and fabrication process for a carbon nanotube field effect transistor is disclosed herein. The structure employs an asymmetric gate which is closer to the source and farther from the drain, which helps to minimize “off current” drain leakage when the drain is biased and the gate is otherwise off. In an embodiment, the source and drain are preferably self aligned to the gate, and preferably the gate is first defined as a conductive sidewall to an etched pad. Dielectric sidewalls are then defined over the gate, which in turn defines the positioning of the source and drain in a predetermined spatial relationship to the gate. In a preferred embodiment, the source and drain comprise conductive sidewalls buttressing the dielectric sidewalls. The channel of the device preferably comprises randomly oriented carbon nanotubes formed on an insulative substrate and isolated from the gate by an insulative layer. In a preferred embodiment, the carbon nanotubes are exposed via the dielectric sidewall etch, thus ensuring the gate's self alignment with the subsequently-formed source and drain.

摘要翻译： 本文公开了一种用于碳纳米管场效应晶体管的结构和制造方法。 该结构采用更接近源极并且离开漏极更远的非对称栅极，这有助于在漏极偏置并且栅极关闭时最小化“截止电流”漏极泄漏。 在一个实施例中，源极和漏极优选地与栅极自对准，并且优选地，栅极首先被定义为蚀刻焊盘的导电侧壁。 然后在栅极上限定介质侧壁，栅极又以与栅极预定的空间关系限定源极和漏极的定位。 在优选实施例中，源极和漏极包括支撑电介质侧壁的导电侧壁。 该器件的沟道优选地包括形成在绝缘衬底上的随机取向的碳纳米管，并通过绝缘层与栅极隔离。 在优选实施例中，通过电介质侧壁蚀刻暴露碳纳米管，从而确保栅极与随后形成的源极和漏极的自对准。

公开(公告)号：US07642204B2

公开(公告)日：2010-01-05

申请号：US10769430

申请日：2004-01-30

申请人： Anand Srinivasan ,  Gurtej Sandhu ,  Ravi Iyer

发明人： Anand Srinivasan ,  Gurtej Sandhu ,  Ravi Iyer

IPC分类号： H01L21/316

CPC分类号： H01L21/02131 ,  C23C16/401 ,  H01L21/02271 ,  H01L21/31629

摘要： In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants. In yet another aspect, the invention includes a method of forming a phosphorus-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising triethoxy fluorosilane, a phosphorus-containing precursor, and ozone within the reaction chamber; and c) depositing a phosphorus-doped silicon oxide having Si—F bonds onto the substrate from the reactants.

摘要翻译： 一方面，本发明包括一种形成绝缘材料的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含Si，F和臭氧的反应物; 以及c）从所述反应物沉积包含氟，硅和氧的绝缘材料到所述衬底上。 另一方面，本发明包括形成具有Si-F键的掺硼氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含硼前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的掺硼氧化硅到所述衬底上。 另一方面，本发明包括形成具有Si-F键的磷掺杂氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含磷前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的磷掺杂的氧化硅到所述衬底上。

公开(公告)号：US20090127656A1

公开(公告)日：2009-05-21

申请号：US12289692

申请日：2008-10-31

申请人： Cem Basceri ,  Gurtej Sandhu

发明人： Cem Basceri ,  Gurtej Sandhu

IPC分类号： H01L29/00

CPC分类号： H01L27/1085

摘要： A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition of a material at pre-determined areas in the dielectric layer.

摘要翻译： 一种具有设置在两个导电电极之间的电介质层的电容器结构，其中所述电介质层包含对应于特定能量状态的至少一个电荷陷阱位置。 能量状态可以用于区分电容器结构的存储器状态，从而允许本发明用作存储器件。 形成陷阱的方法涉及在电介质层中的预定区域处的材料的原子层沉积。

公开(公告)号：US07488665B2

公开(公告)日：2009-02-10

申请号：US10973343

申请日：2004-10-27

申请人： Vishnu K. Agarwal ,  Gurtej Sandhu

发明人： Vishnu K. Agarwal ,  Gurtej Sandhu

IPC分类号： H01L21/20

CPC分类号： H01L27/10817 ,  H01L21/7682 ,  H01L27/0207 ,  H01L27/10852 ,  H01L28/90 ,  H01L28/91

摘要： Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include monolithically-fabricated upright microstructures, i.e., those having large height/width (H/W) ratios, which are mechanical reinforcement against shear forces and the like, by a brace layer that transversely extends between lateral sides of at least two of the free-standing microstructures. The brace layer is formed as a microbridge type structure spanning between the upper ends of the two or more microstructures.

摘要翻译： 公开了具有用于半导体器件的独特三维结构的结构稳定的高电容器。 这些电容器包括单片制造的直立微结构，即具有大的高/宽（H / W）比的那些，它们是抗剪切力等的机械加强，该支撑层横向延伸在至少两个 独立的微结构。 支撑层形成为跨越两个或更多个微结构的上端之间的微桥型结构。

公开(公告)号：US07388248B2

公开(公告)日：2008-06-17

申请号：US10930774

申请日：2004-09-01

申请人： Cem Basceri ,  Gurtej Sandhu

发明人： Cem Basceri ,  Gurtej Sandhu

IPC分类号： H01L29/78 ,  H02H3/22

CPC分类号： H01L27/1085

摘要： A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition,of a material at pre-determined areas in the dielectric layer.

摘要翻译： 一种具有设置在两个导电电极之间的电介质层的电容器结构，其中所述电介质层包含对应于特定能量状态的至少一个电荷陷阱位置。 能量状态可以用于区分电容器结构的存储器状态，从而允许本发明用作存储器件。 形成陷阱的方法涉及在电介质层中预定区域处的材料的原子层沉积。

公开(公告)号：US20080009140A1

公开(公告)日：2008-01-10

申请号：US11483878

申请日：2006-07-10

申请人： Mark Williamson ,  Gurtej Sandhu ,  Justin Arrington

发明人： Mark Williamson ,  Gurtej Sandhu ,  Justin Arrington

IPC分类号： H01L21/461 ,  H01L21/306 ,  H01L21/302

CPC分类号： H01L22/14 ,  G01R31/2898 ,  H01J37/252 ,  H01J37/28 ,  H01J37/3056 ,  H01J2237/24564 ,  H01J2237/24592

摘要： A method of imaging and identifying materials, contamination, fabrication errors, and defects on and below the surface of an integrated circuit (IC) is described. The method may be used in areas smaller than one micron in diameter, and may remove IC layers, either selectively or non-selectively, until a desired depth is obtained. An energetic beam, such as an electron beam, is directed at a selected IC location. The IC has a layer of a solid, fluid or gaseous reactive material, such as a directed stream of a fluorocarbon, formed over the surface of the IC. The energetic beam disassociates the reactive material in or on the region into chemical radicals that chemically attack the surface. The surface may be examined as various layers are selectively removed in the controlled area spot etch, and SEM imaging may then be used to diagnose problems.

摘要翻译： 描述了在集成电路（IC）的表面上和下方成像和识别材料，污染，制造误差和缺陷的方法。 该方法可以用于直径小于一微米的区域，并且可以选择性地或非选择性地去除IC层，直到获得所需的深度。 诸如电子束的能量束被引导到选定的IC位置。 IC具有形成在IC的表面上的固体，流体或气态反应性材料层，例如碳氟化合物的定向流。 能量束将区域中或其上的反应物质分解成化学侵蚀表面的化学自由基。 可以检查表面，因为在受控区域点蚀刻中选择性地去除各种层，然后可以使用SEM成像来诊断问题。

公开(公告)号：US20070264826A1

公开(公告)日：2007-11-15

申请号：US11431269

申请日：2006-05-10

申请人： Gurtej Sandhu

发明人： Gurtej Sandhu

IPC分类号： H01L21/302

CPC分类号： H01L23/5226 ,  H01L21/0337 ,  H01L21/31144 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. The polymer layer is applied uniformly and fills the apertures at different rates depending on the geometry of the apertures, or on the presence or absence of growth accelerating material. The polymer creates spacers for the etching of additional structure in between the spacers. The method is capable of achieving structures smaller than current lithography techniques.

摘要翻译： 提供了一种用于在半导体组件中产生结构的方法。 该方法包括将孔蚀刻到电介质层中，并在该介电层上施加聚合物层。 均匀地施加聚合物层，并根据孔的几何形状，或者存在或不存在生长促进材料，以不同的速率填充孔。 该聚合物产生用于蚀刻间隔物之间​​的附加结构的间隔物。 该方法能够实现比当前光刻技术更小的结构。

公开(公告)号：US20070246703A1

公开(公告)日：2007-10-25

申请号：US11406594

申请日：2006-04-19

申请人： Gurtej Sandhu

发明人： Gurtej Sandhu

IPC分类号： H01L51/00

CPC分类号： B01J37/349 ,  B01J23/745 ,  B01J23/755 ,  B01J31/0215 ,  Y10S977/742

摘要： Embodiments of the present invention are generally directed to a method for disposing nanoparticles on a substrate. In one embodiment, a substrate having a plurality of recesses is provided. In this embodiment, a plurality of nanoparticles is also provided. The nanoparticles include a catalyst material coupled to one or more ligands, and these nanoparticles are disposed within respective recesses of the substrate. In some embodiments, the substrate is processed to form nanostructures, such as nanotubes or nanowires, within the recesses. Devices and systems having such nanostructures are also disclosed.

摘要翻译： 本发明的实施方案通常涉及将纳米颗粒置于基材上的方法。 在一个实施例中，提供具有多个凹部的基板。 在本实施例中，还提供了多个纳米颗粒。 纳米颗粒包括耦合到一个或多个配体的催化剂材料，并且这些纳米颗粒设置在基板的相应凹部内。 在一些实施方案中，在凹陷内处理衬底以形成纳米结构，例如纳米管或纳米线。 还公开了具有这种纳米结构的装置和系统。

公开(公告)号：US07282756B2

公开(公告)日：2007-10-16

申请号：US10665151

申请日：2003-09-22

申请人： Vishnu K. Agarwal ,  Gurtej Sandhu

发明人： Vishnu K. Agarwal ,  Gurtej Sandhu

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10817 ,  H01L21/7682 ,  H01L27/0207 ,  H01L27/10852 ,  H01L28/90 ,  H01L28/91

摘要： Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include monolithically-fabricated upright microstructures, i.e., those having large height/width (H/W) ratios, which are mechanical reinforcement against shear forces and the like, by a brace layer that transversely extends between lateral sides of at least two of the free-standing microstructures. The brace layer is formed as a microbridge type structure spanning between the upper ends of the two or more microstructures.

摘要翻译： 公开了具有用于半导体器件的独特三维结构的结构稳定的高电容器。 这些电容器包括单片制造的直立微结构，即具有大的高/宽（H / W）比的那些，它们是抗剪切力等的机械加强，该支撑层横向延伸在至少两个 独立的微结构。 支撑层形成为跨越两个或更多个微结构的上端之间的微桥型结构。

公开(公告)号：US07279377B2

公开(公告)日：2007-10-09

申请号：US11200694

申请日：2005-08-10

申请人： Neal R. Rueger ,  Gurtej Sandhu

发明人： Neal R. Rueger ,  Gurtej Sandhu

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/7624 ,  H01L27/10844 ,  H01L27/11521 ,  H01L29/7833

摘要： A method suitable for use during fabrication of a semiconductor device such as a dynamic random access memory or a flash programmable read-only memory comprises etching through silicon nitride and pad oxide layers and into a semiconductor wafer to form a trench into the wafer. A shallow trench isolation (STI) layer is formed in the opening in the silicon nitride and in the trench in the wafer which will, under certain conditions, form with an undesirable void. The silicon nitride and pad oxide layers are removed, then an epitaxial silicon layer is formed on the silicon wafer between the STI. A gate/tunnel oxide layer is formed on the epitaxial silicon layer, then a word line is formed over the gate/tunnel oxide. The epitaxial silicon layer ensures that some minimum distance is maintained between the gate/tunnel oxide and the void in the STI. Wafer processing may then be continued to form a completed semiconductor device.

摘要翻译： 适用于半导体器件（例如动态随机存取存储器或闪存可编程只读存储器）的制造期间使用的方法包括通过氮化硅和衬垫氧化物层蚀刻到半导体晶片中以在晶片中形成沟槽。 在硅氮化物的开口和晶片的沟槽中形成浅沟槽隔离（STI）层，这将在某些条件下形成不期望的空隙。 去除氮化硅和衬垫氧化物层，然后在STI之间的硅晶片上形成外延硅层。 在外延硅层上形成栅极/隧道氧化物层，然后在栅极/隧道氧化物上形成字线。 外延硅层确保在栅极/隧道氧化物和STI中的空隙之间保持一些最小距离。 然后可以继续晶片处理以形成完整的半导体器件。