公开(公告)号：US07118999B2

公开(公告)日：2006-10-10

申请号：US10707842

申请日：2004-01-16

申请人： Haining S. Yang ,  Huilong Zhu

发明人： Haining S. Yang ,  Huilong Zhu

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/6653 ,  H01L29/66545 ,  H01L29/7842

摘要： A semiconductor device having a transistor channel with an enhanced stress is provided. To achieve the enhanced stress transistor channel, a nitride film is preferentially formed on the device substrate with little to no nitride on a portion of the gate stack. The nitride film may be preferentially deposited only on the silicon substrate in a non-conformal layer, where little to no nitride is deposited on the upper portions of the gate stack. The nitride film may also be uniformly deposited on the silicon substrate and gate stack in a conformal layer, with the nitride film proximate the upper regions of the gate stack preferentially removed in a later step. In some embodiments, nitride near the top of the gate stack is removed by removing the upper portion of the gate stack. In any of the methods, stress in the transistor channel is enhanced by minimizing nitride deposited on the gate stack, while having nitride deposited on the substrate.

摘要翻译： 提供了具有增强应力的晶体管沟道的半导体器件。 为了实现增强的应力晶体管沟道，在栅极堆叠的一部分上，在器件衬底上优先形成氮化物膜，几乎没有氮化物。 氮化物膜可以优选仅在非保形层中沉积在硅衬底上，其中在栅堆叠的上部上沉积很少至无氮化物。 氮化物膜也可以均匀地沉积在保形层上的硅衬底和栅极堆叠上，其中靠近栅极堆叠的上部区域的氮化物膜在稍后的步骤中优先被去除。 在一些实施例中，通过去除栅极堆叠的上部来去除靠近栅极堆叠顶部的氮化物。 在任何方法中，通过使沉积在栅极堆叠上的氮化物最小化，同时在衬底上沉积氮化物来增强晶体管沟道中的应力。

公开(公告)号：US07102233B2

公开(公告)日：2006-09-05

申请号：US10904060

申请日：2004-10-21

申请人： Haining S. Yang

发明人： Haining S. Yang

IPC分类号： H01L23/52 ,  H01L29/40 ,  H01L21/4763

CPC分类号： H01L21/823871 ,  H01L21/823807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure is provided in which a semiconductor device region has a first portion and a second portion, and a device disposed in the first and second portions. A current conducting member extends horizontally over the first portion but not over the second portion. A dielectric region, having a substantially planar upper surface, is disposed over the member, the dielectric region overlying substantially all of an area of the semiconductor device region that is occupied by the device. A dielectric barrier layer overlies the upper surface of the dielectric region, over substantially all of the area that is occupied by the device. The barrier layer is adapted to substantially prevent diffusion of one or more materials from above the barrier layer into the dielectric region. A contact via extends through the barrier layer and the dielectric region, the contact via in conductive communication with at least one of the member and the second portion of the semiconductor device region.

摘要翻译： 提供一种结构，其中半导体器件区域具有第一部分和第二部分，以及设置在第一和第二部分中的器件。 电流导电构件在第一部分上水平延伸，但不在第二部分上。 具有基本上平面的上表面的电介质区域设置在构件上方，电介质区域覆盖被器件占用的半导体器件区域的基本上所有的区域。 电介质阻挡层覆盖在电介质区域的上表面上，基本上全部由器件所占据的区域。 阻挡层适于基本上防止一种或多种材料从阻挡层上方扩散到电介质区域中。 接触通孔延伸穿过阻挡层和电介质区域，接触通孔与半导体器件区域的构件和第二部分中的至少一个导电连通。

公开(公告)号：US06891192B2

公开(公告)日：2005-05-10

申请号：US10604607

申请日：2003-08-04

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Oleg G. Gluschenkov ,  An L. Steegen ,  Haining S. Yang

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Oleg G. Gluschenkov ,  An L. Steegen ,  Haining S. Yang

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L31/036

CPC分类号： H01L21/84 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

摘要翻译： 提供集成电路的p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 第一应变施加到PFET的沟道区，而不是NFET通过位于仅仅PFET而不是NFET的源极和漏极区域中的晶格不匹配的半导体层，例如硅锗。 提供制造PFET和NFET的工艺。 在区域中蚀刻沟槽以成为PFET的源极和漏极区域，并且将晶格失配的硅锗层外延生长以向与其相邻的PFET的沟道区域施加应变。 可以在硅锗层上生长一层硅层，并从硅层形成硅化物以提供低电阻源极和漏极区域。

公开(公告)号：US06881635B1

公开(公告)日：2005-04-19

申请号：US10708746

申请日：2004-03-23

申请人： Dureseti Chidambarrao ,  Effendi Leobandung ,  Anda C. Mocuta ,  Haining S. Yang ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Effendi Leobandung ,  Anda C. Mocuta ,  Haining S. Yang ,  Huilong Zhu

IPC分类号： C30B25/18 ,  C30B29/06 ,  H01L21/20 ,  H01L21/285 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  C30B23/00 ,  H01L21/36

CPC分类号： H01L29/78696 ,  C30B25/18 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/28562 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/78687

摘要： A planar NFET on a strained silicon layer supported by a SiGe layer achieves reduced external resistance by removing SiGe material outside the transistor body and below the strained silicon layer and replacing the removed material with epitaxial silicon, thereby providing lower resistance for the transistor electrodes and permitting better control over Arsenic diffusion.

摘要翻译： 由SiGe层支撑的应变硅层上的平面NFET通过在晶体管本体外部并且在应变硅层下方除去SiGe材料并且利用外延硅替代去除的材料来实现降低的外部电阻，从而为晶体管电极提供较低电阻并允许 更好地控制砷的扩散。

公开(公告)号：US08809142B2

公开(公告)日：2014-08-19

申请号：US13453165

申请日：2012-04-23

申请人： Deok-Kee Kim ,  Ahmet S. Ozcan ,  Haining S. Yang

发明人： Deok-Kee Kim ,  Ahmet S. Ozcan ,  Haining S. Yang

IPC分类号： H01L21/8238

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.

摘要翻译： 电熔丝结构和方法具有阳极; 熔丝连接（熔丝连接的第一端连接到阳极）; 阴极（与第一端相对的熔断体的第二端连接到阴极）; 和熔丝链上的硅化物层。 硅化物层具有邻近阳极的第一硅化物区域和与阴极相邻的第二硅化物区域。 第二硅化物区域包括不包含在第一硅化物区域内的杂质。 此外，第一硅化物区域比第二硅化物区域薄。

公开(公告)号：US08697521B2

公开(公告)日：2014-04-15

申请号：US12691183

申请日：2010-01-21

申请人： Xinlin Wang ,  Xiangdong Chen ,  Haining S. Yang

发明人： Xinlin Wang ,  Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L27/092

CPC分类号： H01L27/092 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/11 ,  H01L27/1104

摘要： An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation, GIDL and junction leakage.

摘要翻译： 公开了一种改进的SRAM和制造方法。 该方法包括使用氮化物层来封装PFET和逻辑NFET，保护这些器件的栅极免受氧气暴露。 用于SRAM单元中的NFET在退火过程中暴露于氧气，这改变了栅极金属的有效功函数，使得阈值电压增加，而不需要增加掺杂剂浓度，这可能不利地影响问题 例如由于随机掺杂剂波动，GIDL和结泄漏引起的失配。

公开(公告)号：US08476717B2

公开(公告)日：2013-07-02

申请号：US13357757

申请日：2012-01-25

申请人： Robert C. Wong ,  Haining S. Yang

发明人： Robert C. Wong ,  Haining S. Yang

IPC分类号： H01L27/088 ,  H01L27/118

CPC分类号： H01L27/088 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  Y10S257/903

摘要： A semiconductor structure. The semiconductor structure includes: a semiconductor substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface and further includes a first semiconductor body region and a second semiconductor body region; a first gate dielectric region and a second gate dielectric region on top of the first and second semiconductor body regions, respectively; a first gate electrode region on top of the semiconductor substrate and the first gate dielectric region; a second gate electrode region on top of the semiconductor substrate and the second gate dielectric region; and a gate divider region in direct physical contact with the first and second gate electrode regions. The gate divider region does not overlap the first and second gate electrode regions in the reference direction.

摘要翻译： 半导体结构。 半导体结构包括：半导体衬底，其包括限定垂直于顶部衬底表面的参考方向的顶部衬底表面，并且还包括第一半导体本体区域和第二半导体本体区域; 分别在第一和第二半导体本体区域的顶部上的第一栅极电介质区域和第二栅极电介质区域; 在所述半导体衬底和所述第一栅极电介质区域的顶部上的第一栅极电极区域; 在所述半导体衬底和所述第二栅极电介质区域的顶部上的第二栅极电极区域; 以及与第一和第二栅电极区域直接物理接触的栅极分压区域。 栅极分压器区域在参考方向上不与第一和第二栅电极区域重叠。

公开(公告)号：US08173532B2

公开(公告)日：2012-05-08

申请号：US11830090

申请日：2007-07-30

申请人： Robert C. Wong ,  Haining S. Yang

发明人： Robert C. Wong ,  Haining S. Yang

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/461 ,  H01L21/8244 ,  H01L21/302 ,  H01L27/118 ,  H01L27/088 ,  H01L27/11

CPC分类号： H01L27/088 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  Y10S257/903

摘要： A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) first and second semiconductor body regions. The method further includes forming (i) a gate divider region and (ii) a gate electrode layer on top of the semiconductor substrate. The gate divider region is in direct physical contact with gate electrode layer. A top surface of the gate electrode layer and a top surface of the gate divider region are essentially coplanar. The method further includes patterning the gate electrode layer resulting in a first gate electrode region and a second gate electrode region. The gate divider region does not overlap the first and second gate electrode regions in the reference direction.

摘要翻译： 半导体结构及其形成方法。 该方法包括提供包括半导体衬底的半导体结构。 半导体衬底包括（i）限定垂直于顶部衬底表面的参考方向的顶部衬底表面和（ii）第一和第二半导体本体区域。 该方法还包括在半导体衬底的顶部形成（i）栅极分隔区和（ii）栅电极层。 栅极分压器区域与栅极电极层直接物理接触。 栅电极层的顶表面和栅极分隔区的顶表面基本上是共面的。 该方法还包括图案化栅电极层，形成第一栅电极区和第二栅电极区。 栅极分压器区域在参考方向上不与第一和第二栅电极区域重叠。

公开(公告)号：US08083958B2

公开(公告)日：2011-12-27

申请号：US11950600

申请日：2007-12-05

申请人： Wai-Kin Li ,  Haining S. Yang

发明人： Wai-Kin Li ,  Haining S. Yang

IPC分类号： B82Y40/00 ,  H01L21/302

CPC分类号： H01L21/0337 ,  G03F7/0035 ,  H01L21/0273 ,  H01L21/0334 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S977/888 ,  Y10S977/895

摘要： Disclosed are embodiments of a lithographic patterning method that incorporates a combination of photolithography and self-assembling copolymer lithography techniques in order to create, on a substrate, a grid-pattern mask having multiple cells, each with at least one sub-50 nm dimension. The combination of different lithographic techniques further allows for precise registration and overlay of the individual grid-pattern cells with corresponding structures within the substrate. The resulting grid-pattern mask can then be used, in conjunction with directional etch and other processes, to extend the cell patterns into the substrate and, thereby form openings, with at least one sub-50 nm dimension, landing on corresponding in-substrate structures. Once the openings are formed, additional structures can be formed within the openings.

摘要翻译： 公开了包含光刻和自组装共聚物光刻技术的组合的光刻图案化方法的实施例，以便在衬底上形成具有多个单元的栅格图案掩模，每个栅格图案掩模具有至少一个小于50nm的尺寸。 不同光刻技术的组合进一步允许单个栅格图案单元与衬底内的对应结构的精确配准和覆盖。 然后可以结合定向蚀刻和其它工艺将所得到的网格图案掩模用于将单元图形延伸到基底中，从而形成具有至少一个次50nm尺寸的开口，着陆在相应的基底 结构。 一旦形成开口，可以在开口内形成附加结构。

公开(公告)号：US20110260323A1

公开(公告)日：2011-10-27

申请号：US13174841

申请日：2011-07-01

申请人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keich Kwong Hon Wong ,  Haining S. Yang

发明人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keich Kwong Hon Wong ,  Haining S. Yang

IPC分类号： H01L23/52

CPC分类号： H01L21/76841 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.

摘要翻译： 本发明提供了一种互连结构（单镶嵌型或双镶嵌型）及其形成方法，其中在电介质材料的侧壁上存在致密的（即非多孔的）电介质间隔物。 更具体地，本发明的结构包括介电材料，其具有嵌入介电材料中的至少一个开口中的导电材料，其中导电材料通过扩散阻挡层，致密电介质间隔物和任选地， 气隙。 与现有技术的不包括这种致密电介质间隔物的互连结构相比，密集电介质间隔物的存在导致混合互连结构具有改进的可靠性和性能。 此外，本发明的混合互连结构提供了更好的过程控制，这导致了大批量制造的潜力。