公开(公告)号：US20240056400A1

公开(公告)日：2024-02-15

申请号：US17886606

申请日：2022-08-12

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Zsolt Alon Wertheimer ,  Omer Shabtai ,  Barak Goldberg ,  Lion Levi ,  Gil Mey-Tal ,  Bar Or Shapira ,  Dotan David Levi

IPC: H04L47/56 ,  H04L43/0894

CPC classification number: H04L47/56 ,  H04L43/0894

Abstract: Systems, methods, and devices that perform computing operations are provided. In one example, a system includes a least one node, the at least one node having one or more processors, each having associated memory, a clock, a scheduler, the scheduler monitoring one or more of rates, rates of lanes, rates at which packets are sent, times, latencies of packets, topology, communication states, nodes, and packets in the system, an attribute monitor that measures counters for one or more of congestion state, line rate, and communication attributes. A packet scheduler determines a destination node based on information from the scheduler and the attribute monitor, and sends at least a portion of a packet to the destination node.

公开(公告)号：US11876885B2

公开(公告)日：2024-01-16

申请号：US17335122

申请日：2021-06-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Ariel Shahar ,  Shahaf Shuler ,  Ariel Almog ,  Eitan Hirshberg ,  Natan Manevich

IPC: H04L7/00

CPC classification number: H04L7/0091

Abstract: A timing system including timing circuitry which includes an arming queue, a clock work queue, and a clock completion queue. At least the clock work queue is to provide timing information, and the arming queue is to arm the clock work queue. Related apparatus and methods are also provided.

公开(公告)号：US20240015419A1

公开(公告)日：2024-01-11

申请号：US17869932

申请日：2022-07-21

Applicant: Mellanox Technologies, Ltd.

Inventor： Ioannis (Giannis) Patronas ,  Dotan David Levi ,  Wojciech Wasko ,  Paraskevas Bakopoulos ,  Dimitrios Syrivelis ,  Elad Mentovich

IPC: H04Q11/00 ,  H04B10/2575

CPC classification number: H04Q11/0005 ,  H04B10/25753 ,  H04Q2011/0045 ,  H04Q2011/005

Abstract: Network devices and associated methods are provided for synchronization in an optically switched network. The network device includes one or more ports in communication with a plurality of devices via an optical switch. The one or more ports receive a master clock signal having a first frequency from a first device of the plurality of devices. The network device includes a local clock in communication with the one or more ports and operating at a second frequency. The network device includes a synchronization manager in communication with the one or more ports and the local clock and configured to be enabled and disabled. When the synchronization manager is enabled, it receives the master clock signal via the one or more ports and transmits an instruction to the local clock to operate at the first frequency.

公开(公告)号：US20230370305A1

公开(公告)日：2023-11-16

申请号：US17885604

申请日：2022-08-11

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Ariel Almog ,  Bar Shapira

IPC: H04L12/42 ,  G06F1/10 ,  H04L12/43 ,  H04J3/06

CPC classification number: H04L12/422 ,  G06F1/10 ,  H04J3/0667 ,  H04L12/43

Abstract: In one embodiment, a synchronized communication system includes a plurality of network devices, and clock connections to connect the network devices in a closed loop configuration, wherein the network devices are configured to distribute among the network devices a reference clock time from any selected one of the network devices.

公开(公告)号：US20230362097A1

公开(公告)日：2023-11-09

申请号：US17990552

申请日：2022-11-18

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Alex Vaynman ,  Roee Moyal ,  Alex Rosenbaum ,  Stanislav Raitsyn ,  Yuval Atias

IPC: H04L47/25 ,  H04L47/22

CPC classification number: H04L47/25 ,  H04L47/22

Abstract: Aspects of the present disclosure are directed to systems, methods, and computer readable media for dynamic data transfer rate control. One method includes alternating a network device between a plurality of supported data transfer rates that are supported by the network device to achieve an unsupported data transfer rate that is not supported by the network device. Another method includes adding one or more dummy work descriptors to a data stream, and transmitting the data stream including the one or more dummy work descriptors at a supported data transfer rate that is supported by a network device to achieve an effective unsupported data transfer rate that is not supported by the network device.

公开(公告)号：US11711158B2

公开(公告)日：2023-07-25

申请号：US17359667

申请日：2021-06-28

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich ,  Hillel Chapman ,  Roi Geuli ,  Eyal Serbro

IPC: H04J3/06

CPC classification number: H04J3/0661 ,  H04J3/062

Abstract: A network device includes a port, a transmission pipeline and a time-stamping circuit. The port is configured for connecting to a network. The transmission pipeline includes multiple pipeline stages and is configured to process packets and to send the packets to the network via the port. The time-stamping circuit is configured to temporarily suspend at least some processing of at least a given packet in the transmission pipeline, to verify whether a pipeline stage having a variable processing delay, located downstream from the time-stamping circuit, meets an emptiness condition, and, only when the pipeline stage meets the emptiness condition, to time-stamp the given packet and resume the processing of the given packet.

公开(公告)号：US11706014B1

公开(公告)日：2023-07-18

申请号：US17579630

申请日：2022-01-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Ariel Almog ,  Bar Shapira

IPC: H04L7/00

CPC classification number: H04L7/0012

Abstract: In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.

公开(公告)号：US20230185600A1

公开(公告)日：2023-06-15

申请号：US17549949

申请日：2021-12-14

Applicant: Mellanox Technologies, Ltd.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Liron Mula ,  Natan Manevich

IPC: G06F9/48 ,  G06F13/16 ,  G06F1/08

CPC classification number: G06F9/4825 ,  G06F9/485 ,  G06F13/1689 ,  G06F1/08

Abstract: In one embodiment, a system includes a memory, a processing device including a device processor; and a device clock, and a peripheral device including an interface to share data with the processing device, a hardware clock, and processing circuitry to write respective interrupt signaling messages to the memory responsively to respective hardware clock values of the hardware clock, and wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to perform a time-dependent action.

公开(公告)号：US11606157B1

公开(公告)日：2023-03-14

申请号：US17520674

申请日：2021-11-07

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Guy Lederman

IPC: H04J3/06 ,  H04L43/06 ,  H04L43/065 ,  H04L43/067

Abstract: A network node includes a port and circuitry. The port is configured for communicating over a packet network. The circuitry is configured to receive, via the port, a sequence of packets from a peer network node, the sequence of packets including (i) a time-protocol packet and (ii) a transmit-side (TX) time-stamp indicative of a time at which the time-protocol packet was transmitted from the peer network node, to assess a receive-side (RX) traffic pattern over one or more of the received packets in the sequence that precede reception of the time-protocol packet, and to calculate an accuracy measure for the TX time-stamp, based on the assessed RX traffic pattern.

公开(公告)号：US20220360423A1

公开(公告)日：2022-11-10

申请号：US17315396

申请日：2021-05-10

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich ,  Teferet Geula ,  Amit Mandelbaum ,  Ariel Almog

IPC: H04L7/00 ,  H04L12/26 ,  G06N20/00

Abstract: In one embodiment, a processing apparatus includes processing circuitry to process an event, a timestamping unit to generate a timestamp for the event, at least one register to store at least one parameter describing a hardware state of the processing circuitry, and timestamp correction processing circuitry to compute a time value as a correction to the generated timestamp responsively to the at least one parameter.