公开(公告)号：US10891223B2

公开(公告)日：2021-01-12

申请号：US16824314

申请日：2020-03-19

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Graziano Mirichigni ,  Danilo Caraccio

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/1009 ,  G06F3/06 ,  G11C29/52

Abstract: Devices and techniques for storage class memory status are disclosed herein. A storage portion characteristics data structure is maintained. Here, the data structure includes an array of elements—where each element is sized to contain a reference to a storage portion in a storage class memory storage device, a first pointer to a first element in the array of elements, a second pointer to a second element in the array of elements, and a third pointer to a third element in the array of elements. The data structure includes a direction of pointer motion in which the second pointer precedes the third pointer and the first pointer precedes the second pointer with respect to the direction of pointer motion. A write request is performed to a storage portion reference retrieved from the first element. The first pointer is then advanced.

公开(公告)号：US20200335159A1

公开(公告)日：2020-10-22

申请号：US16922883

申请日：2020-07-07

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Marco Sforzin ,  Alessandro Orlando

IPC: G11C11/56 ,  G11C16/32 ,  G11C16/30 ,  G11C8/14 ,  G11C16/08 ,  G11C13/00 ,  G11C7/14

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data in memory cells. Subsequently, reading the encoded user data may be carried out by applying a read voltage to the memory cells while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. The auto-referenced read may identify a particular switching event that correlates to a median threshold voltage value of the subset of the memory cells. Then, the auto-referenced read may determine a reference voltage that takes into account a statistical property of threshold voltage distribution of the subset of the memory cells. The auto-referenced read may identify a time duration to maintain the read voltage based on determining the reference voltage. When the time duration expires, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

公开(公告)号：US20200294586A1

公开(公告)日：2020-09-17

申请号：US16791764

申请日：2020-02-14

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Paolo Amato ,  Federico Pio ,  Alessandro Orlando ,  Marco Sforzin

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C11/56

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

公开(公告)号：US20200218645A1

公开(公告)日：2020-07-09

申请号：US16824314

申请日：2020-03-19

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Graziano Mirichigni ,  Danilo Caraccio

IPC: G06F12/02 ,  G06F3/06 ,  G11C29/52 ,  G06F12/1009

Abstract: Devices and techniques for storage class memory status are disclosed herein. A storage portion characteristics data structure is maintained. Here, the data structure includes an array of elements—where each element is sized to contain a reference to a storage portion in a storage class memory storage device, a first pointer to a first element in the array of elements, a second pointer to a second element in the array of elements, and a third pointer to a third element in the array of elements. The data structure includes a direction of pointer motion in which the second pointer precedes the third pointer and the first pointer precedes the second pointer with respect to the direction of pointer motion. A write request is performed to a storage portion reference retrieved from the first element. The first pointer is then advanced.

公开(公告)号：US10600480B2

公开(公告)日：2020-03-24

申请号：US16536120

申请日：2019-08-08

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Paolo Amato ,  Federico Pio ,  Alessandro Orlando ,  Marco Sforzin

IPC: G11C7/10 ,  G11C13/00 ,  G11C11/56 ,  H01L45/00 ,  H01L27/24 ,  G11C7/06

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

公开(公告)号：US10566052B2

公开(公告)日：2020-02-18

申请号：US15853328

申请日：2017-12-22

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Marco Sforzin ,  Alessandro Orlando

IPC: G11C11/22 ,  G11C11/56 ,  G11C16/32 ,  G11C16/30 ,  G11C8/14 ,  G11C16/08

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data in memory cells. Subsequently, reading the encoded user data may be carried out by applying a read voltage to the memory cells while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. The auto-referenced read may identify a particular switching event that correlates to a median threshold voltage value of the subset of the memory cells. Then, the auto-referenced read may determine a reference voltage that takes into account a statistical property of threshold voltage distribution of the subset of the memory cells. The auto-referenced read may identify a time duration to maintain the read voltage based on determining the reference voltage. When the time duration expires, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

公开(公告)号：US20190198099A1

公开(公告)日：2019-06-27

申请号：US15853364

申请日：2017-12-22

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Paolo Amato ,  Federico Pio ,  Alessandro Orlando ,  Marco Sforzin

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/004 ,  G11C7/06 ,  G11C7/1006 ,  G11C13/0004 ,  G11C2013/0054 ,  H01L27/2481 ,  H01L45/06

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

公开(公告)号：US20190171567A1

公开(公告)日：2019-06-06

申请号：US16272945

申请日：2019-02-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Luca Porzio ,  Erminio Di Martino ,  Giacomo Bernardi ,  Domenico Monteleone ,  Stefano Zanardi ,  Chee Weng Tan ,  Sebastien LeMarie ,  Andre Klindworth

IPC: G06F12/0804 ,  G06F13/00 ,  G06F13/16 ,  G06F12/0891

Abstract: Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus mau include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.

公开(公告)号：US20190018618A1

公开(公告)日：2019-01-17

申请号：US16136101

申请日：2018-09-19

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Graziano Mirichigni ,  Danilo Caraccio ,  Luca Porzio ,  Antonino Pollio

IPC: G06F3/06 ,  G06F12/00

Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.

公开(公告)号：US10067764B2

公开(公告)日：2018-09-04

申请号：US15646874

申请日：2017-07-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio ,  Chee Weng Tan ,  Sebastien Lemarie ,  Andre Klindworth

IPC: G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C13/00 ,  G06F9/30

Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.