公开(公告)号：US11755409B2

公开(公告)日：2023-09-12

申请号：US17869775

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G06F11/10 ,  G06F11/30 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/1048 ,  G06F11/3037

Abstract: Methods, systems, and devices for internal error correction for memory devices are described. A memory device may perform a read operation at a memory array having a data partition and an error check partition and may obtain a first set of bits from the data partition and a second set of bits from the error check partition. The memory device may determine a first error detection result based on a value of a determined syndrome. The memory device may obtain a parity bit from the first set of bits and determine a second error detection result based on a comparison of the parity bit with a second function of the subset of the first set of bits. The memory device may transmit the first set of bits to a host device based at least in part on the first and second error detection results.

公开(公告)号：US11720443B2

公开(公告)日：2023-08-08

申请号：US17518160

申请日：2021-11-03

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G06F11/10 ,  G11C11/409 ,  G06F12/14

CPC classification number: G06F11/1068 ,  G06F11/102 ,  G06F11/1016 ,  G06F12/1425 ,  G11C11/409

Abstract: Methods, systems, and devices for error correction management are described. A system may include a memory device that supports internal detection and correction of corrupted data, and whether such detection and correction functionality is operating properly may be evaluated. A known error may be included (e.g., intentionally introduced) into either data stored at the memory device or an associated error correction codeword, among other options, and data or other indications subsequently generated by the memory device may be evaluated for correctness in view of the error. Thus, either the memory device or a host device coupled with the memory device, among other devices, may determine whether error detection and correction functionality internal to the memory device is operating properly.

公开(公告)号：US11714711B2

公开(公告)日：2023-08-01

申请号：US17721462

申请日：2022-04-15

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F11/10 ,  G06F11/32 ,  G06F11/30 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/1044 ,  G06F11/3037 ,  G06F11/326

Abstract: Methods, systems, and devices for a memory device with status feedback for error correction are described. For example, during a read operation, a memory device may perform an error correction operation on first data read from a memory array of the memory device. The error correction operation may generate second data and an indicator of a state of error corresponding to the second data. In one example, the indicator may indicate one of multiple possible states of error. In another example, the indicator may indicate a corrected error or no detectable error. The memory device may output the first or second data and the indicator of the state of error during a same burst interval. The memory device may output the data on a first channel and the indicator of the state of error on a second channel.

公开(公告)号：US20230205620A1

公开(公告)日：2023-06-29

申请号：US17889203

申请日：2022-08-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/073

Abstract: Methods, systems, and devices for coordinated error protection are described. A set of data and an indication of whether a first management procedure performed by a memory device on the set of data detected one or more errors in the set of data may be received at a host device. At the host device, a second error management procedure may be performed on the set of data received from the memory device. Based on the received indication and the second error management procedure, multiple bits indicating whether one or more errors associated with the set of data were detected at the memory device, the host device, or both may be generated. The set of data may be validated or discarded based on the multiple bits.

公开(公告)号：US11663075B2

公开(公告)日：2023-05-30

申请号：US17470584

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: H03M13/00 ,  G06F11/10 ,  G11C29/44 ,  G11C7/10 ,  G11C29/42 ,  G06F11/07

CPC classification number: G06F11/1048 ,  G06F11/0787 ,  G06F11/1068 ,  G11C7/1045 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, systems, and apparatus to selectively implement single-error correcting (SEC) operations or single-error correcting and double-error detecting (SECDED) operations, without noticeably impacting die size, for information received from a host device. For example, a host device may indicate that a memory system is to implement SECDED operations using one or more communications (e.g., messages). In another example, the memory system may be hardwired to perform SECDED for certain options. The memory system may adapt circuitry associated with SEC operations to implement SECDED operations without noticeably impacting die size. To implement SECDED operations using SEC circuitry, the memory system may include some additional circuitry to repurpose the SEC circuitry for SECDED operations.

公开(公告)号：US20230161511A1

公开(公告)日：2023-05-25

申请号：US18100654

申请日：2023-01-24

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G06F3/06 ,  G06F21/79

CPC classification number: G06F3/0659 ,  G06F3/0673 ,  G06F3/0604 ,  G06F21/79 ,  G06F12/1441

Abstract: Methods, systems, and devices for command block management are described. A memory device may receive a command (e.g., from a host device). The memory device may determine whether the command is defined by determining if the command is included within a set of defined commands. In the case that a received command is absent from the set of defined commands (e.g., the command is undefined), the memory device may block the command from being decoded for execution by the memory device. In some cases, the memory device may switch from a first operation mode to a second operation mode based on receiving an undefined command. The second operation mode may restrict an operation of the memory device, while the first mode may be less restrictive, in some cases. Additionally or alternatively, the memory device may indicate the undefined command to another device (e.g., the host device).

公开(公告)号：US11650943B2

公开(公告)日：2023-05-16

申请号：US16578076

申请日：2019-09-20

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G06F11/00 ,  G06F13/16 ,  G06F11/07 ,  G06F13/38

CPC classification number: G06F13/1678 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F13/385

Abstract: Methods, systems, and devices for flexible bus management are described. A memory device may transfer data between the memory device and another device (e.g., host device) using a bus including a plurality of data pins. The memory device may transfer data according to a first bus configuration (e.g., according to a first width corresponding to using all of the data pins). After receiving an indication to adjust the configuration, the memory device may adjust the first bus configuration to a second bus configuration where the bus operates according to a second width (e.g., using a subset of the data pins). The memory device may adjust the bus width between the other device and the memory device without adjusting an internal bus width of the memory device (e.g., internal busses that transfer data from the data pins to various components within the memory device).

公开(公告)号：US11644977B2

公开(公告)日：2023-05-09

申请号：US17365013

申请日：2021-07-01

Applicant: Micron Technology, Inc.

Inventor： Scott D. Van De Graaff ,  Todd Jackson Plum ,  Scott E. Schaefer ,  Aaron P. Boehm ,  Mark D. Ingram

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for life expectancy monitoring for memory devices are described. Some memory devices may degrade over time, and this degradation may include or refer to a reduction of an ability of the memory device to reliably store, read, process, or communicate information, among other degradation. In accordance with examples as disclosed herein, a system may include components configured for monitoring health or life expectancy of the memory device, such as components that perform comparisons between signals or other operating characteristics resulting from operating at the memory device and one or more threshold values that may be indicative of a life expectancy of the memory device. In various examples, a memory device may perform a subsequent operation based on such a comparison, or may provide an indication of a life expectancy to a host device based on one or more comparisons or determinations about health or life expectancy.

公开(公告)号：US11600355B2

公开(公告)日：2023-03-07

申请号：US17365003

申请日：2021-07-01

Applicant: Micron Technology, Inc.

Inventor： Mark D. Ingram ,  Todd Jackson Plum ,  Scott E. Schaefer ,  Aaron P. Boehm ,  Scott D. Van De Graaff

IPC: G11C29/44 ,  G11C29/12 ,  G06F12/02

Abstract: Methods, systems, and devices for monitoring and adjusting access operations at a memory device are described to support integrating monitors or sensors for detecting memory device health issues, such as those resulting from device access or wear. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a metric related to access operations for the memory device. The memory device may use the metric (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.

公开(公告)号：US20230065593A1

公开(公告)日：2023-03-02

申请号：US17821413

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer ,  Scott D. Van De Graaff ,  Mark D. Ingram ,  Todd Jackson Plum

IPC: G11C7/24 ,  G11C7/04 ,  G11C7/10

Abstract: Methods, systems, and devices for memory traffic monitoring are described. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a characteristic related to an operational bias of circuits of the memory device. The memory device may use the characteristic (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.