公开(公告)号：US07268043B2

公开(公告)日：2007-09-11

申请号：US11565127

申请日：2006-11-30

申请人： Nak-Jin Son ,  Ji-Young Kim

发明人： Nak-Jin Son ,  Ji-Young Kim

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/331

CPC分类号： H01L29/66651 ,  H01L27/10873 ,  H01L29/1041 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/78

摘要： A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.

摘要翻译： 公开了一种半导体器件及其制造方法。 在半导体衬底的有源区中形成沟槽。 掺杂层形成在沟槽的内壁上。 沟槽填充有第一半导体层。 在第一半导体层和基板上形成栅极绝缘层。 在栅极绝缘层上形成两个栅电极，使得沟槽位于两个栅电极之间。 在每个栅电极的两侧的基板中形成第一和第二杂质区。 由于掺杂层局部地形成在沟槽区域中，源极和漏极区域与重掺杂层完全分离，以削弱PN结的电场，从而改善了源极和漏极之间的刷新并防止穿透。

公开(公告)号：US20070190716A1

公开(公告)日：2007-08-16

申请号：US11691044

申请日：2007-03-26

申请人： Ji-Young Kim

发明人： Ji-Young Kim

IPC分类号： H01L21/8242

CPC分类号： H01L29/66621 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823487

摘要： Provided is a method of fabricating a recess transistor in an integrated circuit device. In the provided method, a device isolation region, which contacts to the sidewall of a gate trench and a substrate region remaining between the sidewall of the device isolation region and the sidewall of the gate trench, is etched to expose the remaining substrate region. Thereafter, the exposed portion of the remaining substrate region is removed to form a substantially flat bottom of the gate trench. The recess transistor manufactured by the provided method has the same channel length regardless of the locations of the recess transistor in an active region.

摘要翻译： 提供了一种在集成电路器件中制造凹槽晶体管的方法。 在所提供的方法中，蚀刻与栅极沟槽的侧壁接触的器件隔离区域和残留在器件隔离区域的侧壁与栅极沟槽的侧壁之间的衬底区域，以露出剩余的衬底区域。 此后，去除剩余的衬底区域的暴露部分以形成栅极沟槽的基本平坦的底部。 通过所提供的方法制造的凹槽晶体管具有相同的沟道长度，而与有源区中的凹槽晶体管的位置无关。

公开(公告)号：US20070096185A1

公开(公告)日：2007-05-03

申请号：US11641845

申请日：2006-12-20

申请人： Ji-Young Kim ,  Chang-Hyun Cho ,  Soo-Ho Shin ,  Tae-Young Chung

发明人： Ji-Young Kim ,  Chang-Hyun Cho ,  Soo-Ho Shin ,  Tae-Young Chung

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119 ,  H01L21/8242

CPC分类号： H01L21/28114 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

摘要： A self-aligned inner gate recess channel in a semiconductor substrate includes a recess trench formed in an active region of the substrate, a gate dielectric layer formed on a bottom portion of the recess trench, recess inner sidewall spacers formed on sidewalls of the recess trench, a gate formed in the recess trench so that an upper portion of the gate protrudes above an upper surface of the substrate, wherein a thickness of the recess inner sidewall spacers causes a center portion of the gate to have a smaller width than the protruding upper portion and a lower portion of the gate, a gate mask formed on the gate layer, gate sidewall spacers formed on the protruding upper portion of gate and the gate mask, and a source/drain region formed in the active region of the substrate adjacent the gate sidewall spacers.

摘要翻译： 半导体衬底中的自对准内门凹槽通道包括形成在衬底的有源区中的凹槽，形成在凹槽的底部的栅介电层，形成在凹槽沟槽的侧壁上的凹陷内侧壁 形成在所述凹槽中的栅极，使得所述栅极的上部突出于所述基板的上表面之上，其中所述凹陷内侧壁间隔物的厚度使得所述栅极的中心部分具有比所述突出的上部 栅极的部分和下部，形成在栅极层上的栅极掩模，形成在栅极的突出上部上的栅极侧壁间隔物和栅极掩模，以及形成在邻近基板的基板的有源区域中的源极/漏极区域 门侧壁间隔件。

公开(公告)号：US07211482B2

公开(公告)日：2007-05-01

申请号：US11141312

申请日：2005-06-01

申请人： Ji-Young Kim ,  Jin-Jun Park

发明人： Ji-Young Kim ,  Jin-Jun Park

IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L21/336 ,  H01L21/8228

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834 ,  H01L2924/3011

摘要： A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.

摘要翻译： 半导体器件的存储单元及其形成方法，其中存储单元包括具有有源区和场区的衬底，形成在衬底上的栅极层，栅层包括形成在有源区上的多个存取栅极 衬底的区域和形成在衬底的场区域上的多个通过栅极，形成在相邻栅极和存取栅极之间的第一自对准接触区域和形成在相邻栅极之间的第二自对准接触区域，其中宽度 每个第一自对准接触区域的宽度大于第二自对准接触区域中的每一个的宽度。

公开(公告)号：US20070069265A1

公开(公告)日：2007-03-29

申请号：US11503130

申请日：2006-08-14

申请人： Ji-Young Kim ,  Jin-Jun Park

发明人： Ji-Young Kim ,  Jin-Jun Park

IPC分类号： H01L29/94

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834 ,  H01L2924/3011

摘要： A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.

摘要翻译： 半导体器件的存储单元及其形成方法，其中存储单元包括具有有源区和场区的衬底，形成在衬底上的栅极层，栅层包括形成在有源区上的多个存取栅极 衬底的区域和形成在衬底的场区域上的多个通过栅极，形成在相邻栅极和存取栅极之间的第一自对准接触区域和形成在相邻栅极之间的第二自对准接触区域，其中宽度 每个第一自对准接触区域的宽度大于第二自对准接触区域中的每一个的宽度。

公开(公告)号：US20070052013A1

公开(公告)日：2007-03-08

申请号：US11449959

申请日：2006-06-09

申请人： Hyun-Ki Kim ,  Jung-Hwa Lee ,  Ji-Young Kim

发明人： Hyun-Ki Kim ,  Jung-Hwa Lee ,  Ji-Young Kim

IPC分类号： H01L29/94

CPC分类号： H01L29/945 ,  H01L27/0207 ,  H01L27/0805 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/66181 ,  H01L29/66621 ,  H01L29/78

摘要： A semiconductor device having a decoupling capacitor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region. At least one channel trench is disposed in the cell region of the semiconductor substrate. At least one first capacitor trench is disposed in the first peripheral circuit region of the semiconductor substrate, and at least one second capacitor trench is disposed in the second peripheral circuit region of the semiconductor substrate. A gate electrode is disposed in the cell region of the semiconductor substrate and fills the channel trench. A first upper electrode is disposed in the first peripheral circuit region of the semiconductor substrate and fills at least the first capacitor trench. A second upper electrode is disposed in the second peripheral circuit region of the semiconductor substrate and fills at least the second capacitor trench. A gate dielectric layer is interposed between the channel trench and the gate electrode. A first dielectric layer is interposed between the semiconductor substrate of the first peripheral circuit region having the first capacitor trench and the first upper electrode and has the same thickness as the gate dielectric layer. A second dielectric layer is interposed between the semiconductor substrate of the second peripheral circuit region having the second capacitor trench and the second upper electrode and has a different thickness from the first dielectric layer.

摘要翻译： 提供具有去耦电容器的半导体器件及其制造方法。 半导体器件包括具有单元区域，第一外围电路区域和第二外围电路区域的半导体衬底。 至少一个通道沟槽设置在半导体衬底的单元区域中。 至少一个第一电容器沟槽设置在半导体衬底的第一外围电路区域中，并且至少一个第二电容器沟槽设置在半导体衬底的第二外围电路区域中。 栅电极设置在半导体衬底的单元区域中并填充沟槽。 第一上电极设置在半导体衬底的第一外围电路区域中，并且填充至少第一电容器沟槽。 第二上电极设置在半导体衬底的第二外围电路区域中，并且填充至少第二电容器沟槽。 栅极电介质层介于通道沟槽和栅电极之间。 在具有第一电容器沟槽的第一外围电路区域的半导体衬底和第一上电极之间插入第一电介质层，并且具有与栅极电介质层相同的厚度。 在具有第二电容器沟槽的第二外围电路区域的半导体衬底和第二上部电极之间插入第二电介质层，并且具有与第一电介质层不同的厚度。

公开(公告)号：US07154144B2

公开(公告)日：2006-12-26

申请号：US10730996

申请日：2003-12-10

申请人： Ji-Young Kim ,  Chang-Hyun Cho ,  Soo-Ho Shin ,  Tae-Young Chung

发明人： Ji-Young Kim ,  Chang-Hyun Cho ,  Soo-Ho Shin ,  Tae-Young Chung

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66553 ,  H01L29/4238 ,  H01L29/66621 ,  H01L29/7834

摘要： A self-aligned inner gate recess channel in a semiconductor substrate includes a recess trench formed in an active region of the substrate, a gate dielectric layer formed on a bottom portion of the recess trench, recess inner sidewall spacers formed on sidewalls of the recess trench, a gate formed in the recess trench so that an upper portion of the gate protrudes above an upper surface of the substrate, wherein a thickness of the recess inner sidewall spacers causes a center portion of the gate to have a smaller width than the protruding upper portion and a lower portion of the gate, a gate mask formed on the gate layer, gate sidewall spacers formed on the protruding upper portion of gate and the gate mask, and a source/drain region formed in the active region of the substrate adjacent the gate sidewall spacers.

摘要翻译： 半导体衬底中的自对准内门凹槽通道包括形成在衬底的有源区中的凹槽，形成在凹槽的底部的栅介电层，形成在凹槽沟槽的侧壁上的凹陷内侧壁 形成在所述凹槽中的栅极，使得所述栅极的上部突出于所述基板的上表面之上，其中所述凹陷内侧壁间隔物的厚度使得所述栅极的中心部分具有比所述突出的上部 栅极的部分和下部，形成在栅极层上的栅极掩模，形成在栅极的突出上部上的栅极侧壁间隔物和栅极掩模，以及形成在邻近基板的基板的有源区域中的源极/漏极区域 门侧壁间隔件。

公开(公告)号：US07091072B2

公开(公告)日：2006-08-15

申请号：US10971353

申请日：2004-10-22

申请人： Yong-jik Park ,  Ji-Young Kim

发明人： Yong-jik Park ,  Ji-Young Kim

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/66651 ,  H01L29/0649 ,  H01L29/105 ,  H01L29/66575

摘要： Provided are a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes an isolation insulating film, an epitaxial silicon layer, a junction blocking insulating film, a gate stack, and source and drain junctions. The isolation insulating film is formed on a semiconductor substrate to define an active area. The epitaxial silicon layer is formed in the active area of the semiconductor substrate and surrounded by the isolation insulating film. The junction blocking insulating film is formed in the epitaxial silicon layer. The gate stack is formed over the epitaxial silicon layer so that the junction blocking insulating film is buried under approximately the center of the gate stack. The source and drain junctions are formed adjacent the sidewalls of the gate stack. Accordingly, a short circuit between source/drain junctions in a bulk area caused by the unwanted diffusion of the junctions can be prevented.

公开(公告)号：US20060113590A1

公开(公告)日：2006-06-01

申请号：US11285558

申请日：2005-11-22

申请人： Ji-Hae Kim ,  Ji-Young Kim ,  Jong-Chul Park ,  Yong-Sun Ko ,  Sang-Sup Jeong

发明人： Ji-Hae Kim ,  Ji-Young Kim ,  Jong-Chul Park ,  Yong-Sun Ko ,  Sang-Sup Jeong

IPC分类号： H01L29/94

CPC分类号： H01L29/66621 ,  H01L29/7834

摘要： An isolation layer having a first depth is formed from an upper face of a substrate. Source/drain regions including junctions are formed in the substrate. Each of the junctions has a second depth substantially smaller than the first depth. A first recess is formed in the substrate by a first etching process. A protection layer pattern is formed on a sidewall of the first recess. A second recess is formed beneath the first recess. The second recess has a width substantially larger than that of the first recess. The second recess is formed by a second etching process using an etching gas containing an SF6 gas, a Cl2 gas and an O2 gas. A gate insulation layer is formed on surfaces of the first and the second recesses. The second recess having an enlarged shape may reduce a width of the junction between the gate electrode and the isolation layer so that a leakage current generated through the junction may decrease.

摘要翻译： 具有第一深度的隔离层由衬底的上表面形成。 在衬底中形成包括结的源/漏区。 每个结点具有比第一深度基本上小的第二深度。 通过第一蚀刻工艺在衬底中形成第一凹部。 在第一凹部的侧壁上形成保护层图案。 在第一凹部下面形成第二凹部。 第二凹部的宽度显着大于第一凹部的宽度。 第二凹槽通过使用含有SF 6气体，Cl 2气体和O 2气体的蚀刻气体的第二蚀刻工艺形成 。 在第一和第二凹部的表面上形成栅极绝缘层。 具有放大形状的第二凹部可以减小栅电极和隔离层之间的结的宽度，使得通过结可以产生的漏电流可能减小。

公开(公告)号：US07052983B2

公开(公告)日：2006-05-30

申请号：US10688017

申请日：2003-10-16

申请人： Byung-Jun Park ,  Ji-Young Kim

发明人： Byung-Jun Park ,  Ji-Young Kim

IPC分类号： H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： Wirings including first conductive layer patterns and insulating mask layer patterns are formed on a substrate. Insulating spacers are formed on sidewalls of the wirings. Self-aligned contact pads including portions of a second conductive layer are formed to contact with surfaces of the insulating spacers and to fill up a gap between the wirings. An interlayer dielectric layer is formed on the substrate where the contact pads are formed and is then partially etched to form contact holes exposing the contact pads. A selective epitaxial silicon layer is formed on the contact pads exposed through the contact holes to cover the insulating mask layer patterns. Thus, a short-circuit between the lower wiring and an upper wiring formed in the contact holes is prevented.

摘要翻译： 在基板上形成包括第一导电层图案和绝缘掩模层图案的布线。 绝缘垫片形成在布线的侧壁上。 形成包括第二导电层的部分的自对准接触焊盘与绝缘间隔物的表面接触并填充布线之间的间隙。 在形成接触焊盘的基板上形成层间电介质层，然后将其部分地蚀刻以形成暴露接触焊盘的接触孔。 在通过接触孔暴露的接触焊盘上形成选择性外延硅层以覆盖绝缘掩模层图案。 因此，防止下布线和形成在接触孔中的上布线之间的短路。