公开(公告)号：US20100296212A1

公开(公告)日：2010-11-25

申请号：US12538860

申请日：2009-08-10

Applicant: Yung-Chih Liang ,  Chih-Ting Yeh ,  Shih-Hung Chen

Inventor： Yung-Chih Liang ,  Chih-Ting Yeh ,  Shih-Hung Chen

IPC: H02H9/04

CPC classification number: H01L27/0285 ,  H01L2924/0002 ,  H02H9/046 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) clamp circuit is provided. The ESD clamp circuit includes a first resistor, a second resistor, a first transistor, a second transistor, and a third transistor. A clamp device of the ESD clamp circuit is implemented by the third transistor. A parasitic capacitor of the third transistor forms a detection scheme along with the second resistor to detect the ESD. The first resistor, the second resistor, the first transistor, and the second transistor form a feedback scheme to control the third transistor for discharging the ESD current.

Abstract translation: 提供静电放电（ESD）钳位电路。 ESD钳位电路包括第一电阻器，第二电阻器，第一晶体管，第二晶体管和第三晶体管。 ESD钳位电路的钳位装置由第三晶体管实现。 第三晶体管的寄生电容器与第二电阻器一起形成检测方案以检测ESD。 第一电阻器，第二电阻器，第一晶体管和第二晶体管形成反馈方案以控制用于放电ESD电流的第三晶体管。

公开(公告)号：US07726987B2

公开(公告)日：2010-06-01

申请号：US12211062

申请日：2008-09-15

Applicant: Shih-Hung Chen

Inventor： Shih-Hung Chen

IPC: H01R13/44

CPC classification number: H05K5/0265 ,  H05K5/0282 ,  Y10S439/945

Abstract: A card fixer is suitable to assist a card to be fixed in a slot of an electronic device. The card fixer includes a body and a clipping structure, wherein the body has a first side and a second side parallel to the first side. A hook is disposed on the first side of the body. The clipping structure extends out of the second side of the body for clipping the card thereon. When the clipping structure of the card fixer clips the card and the assembly of the card fixer with the card is inserted into the slot, the hook is locked on an inside wall of the slot.

Abstract translation: 卡固定器适合于帮助卡固定在电子设备的槽中。 卡定位器包括主体和夹持结构，其中主体具有平行于第一侧的第一侧和第二侧。 钩体设置在身体的第一侧。 夹持结构从身体的第二侧延伸出来，用于将卡夹在其上。 当卡片固定器的剪辑结构夹住卡片时，卡片固定器与卡片的组合被插入到插槽中，钩子被锁定在插槽的内壁上。

公开(公告)号：US07514288B2

公开(公告)日：2009-04-07

申请号：US11155451

申请日：2005-06-17

Applicant: Hsiang Lan Lung ,  Shih-Hung Chen

Inventor： Hsiang Lan Lung ,  Shih-Hung Chen

IPC: H01L21/06

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

Abstract: A method for manufacturing a memory device comprises forming an electrode layer on a substrate which comprises circuitry made using front-end-of-line procedures. The electrode layer includes a first electrode and a second electrode, and an insulating member between the first and second electrodes for each phase change memory cell to be formed. A bridge of memory material is formed on the top surface of the electrode layer across the insulating member for each memory cell to be formed. An access structure over the electrode layer is made by forming a patterned conductive layer over said bridge, and forming a contact between said first electrode and said patterned conductive layer.

Abstract translation: 一种用于制造存储器件的方法包括在衬底上形成电极层，该电极层包括使用前端工艺制造的电路。 电极层包括第一电极和第二电极，以及用于要形成的每个相变存储器单元的第一和第二电极之间的绝缘构件。 在要形成的每个存储器单元的绝缘构件上，在电极层的顶表面上形成记忆材料桥。 通过在所述桥上形成图案化的导电层，并在所述第一电极和所述图案化的导电层之间形成接触来形成电极层上方的访问结构。

公开(公告)号：US07450411B2

公开(公告)日：2008-11-11

申请号：US11459106

申请日：2006-07-21

Applicant: Hsiang Lan Lung ,  Shih-Hung Chen

Inventor： Hsiang Lan Lung ,  Shih-Hung Chen

IPC: G11C11/00

CPC classification number: H01L45/144 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1675 ,  H01L45/1691

Abstract: A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change bridge positioned between and electrically coupling the opposed sides of the electrodes to one another. The phase change bridge has a length, a width and a thickness. The width, the thickness and the length are less than a minimum photolithographic feature size of the process used to form the phase change memory cell. The size of the photoresist masks used in forming the memory cell may be reduced so that the width and the length of the phase change bridge are each less than the minimum photolithographic feature size.

Abstract translation: 相变存储器件包括具有第一和第二电极的光刻形成的相变存储器单元和位于电极的相对侧之间并将电极彼此电耦合的相变桥。 相变桥具有长度，宽度和厚度。 宽度，厚度和长度小于用于形成相变存储单元的工艺的最小光刻特征尺寸。 可以减小用于形成存储单元的光致抗蚀剂掩模的尺寸，使得相变桥的宽度和长度均小于最小光刻特征尺寸。

公开(公告)号：US20080165569A1

公开(公告)日：2008-07-10

申请号：US11619625

申请日：2007-01-04

Applicant: Chieh-Fang Chen ,  Shih-Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

Inventor： Chieh-Fang Chen ,  Shih-Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

IPC: G11C11/00 ,  H01L21/06 ,  H01L21/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625

Abstract: A memory cell comprises a first electrode, a second electrode and a composite material. The composite material electrically couples the first electrode to the second electrode. Moreover, the composite material comprises a phase change material and a resistor material. At least a portion of the phase change material is operative to switch between a substantially crystalline phase and a substantially amorphous phase in response to an application of a switching signal to at least one of the first and second electrodes. In addition, the resistor material has a resistivity lower than that of the phase change material when the phase change material is in the substantially amorphous phase.

Abstract translation: 存储单元包括第一电极，第二电极和复合材料。 复合材料将第一电极电耦合到第二电极。 此外，复合材料包括相变材料和电阻材料。 响应于向第一和第二电极中的至少一个施加开关信号，相变材料的至少一部分可操作以在基本上结晶相和基本非晶相之间切换。 此外，当相变材料处于基本非晶相时，电阻材料的电阻率低于相变材料的电阻率。

公开(公告)号：US20080105862A1

公开(公告)日：2008-05-08

申请号：US11959708

申请日：2007-12-19

Applicant: Hsiang Lan Lung ,  Shih-Hung Chen

Inventor： Hsiang Lan Lung ,  Shih-Hung Chen

IPC: H01L45/00

CPC classification number: H01L45/1226 ,  G11C13/0004 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1691

Abstract: A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member. An array of such memory cells is provided. In the array, a plurality of electrode members and insulating members therebetween comprise an electrode layer on an integrated circuit. The bridges of memory material have sub-lithographic dimensions.

Abstract translation: 一种存储器件，包括具有顶侧的第一电极，具有顶侧的第二电极和位于第一电极和第二电极之间的绝缘构件。 绝缘构件在第一电极的顶侧附近和第二电极的顶侧之间具有在第一和第二电极之间的厚度。 记忆材料桥跨越绝缘构件，并且在绝缘构件之间限定了第一和第二电极之间的电极间路径。 提供这样的存储单元阵列。 在阵列中，多个电极构件和绝缘构件包括集成电路上的电极层。 记忆材料的桥梁具有亚光刻尺寸。

公开(公告)号：US20080062597A1

公开(公告)日：2008-03-13

申请号：US11717948

申请日：2007-03-13

Applicant: Shih-Hung Chen ,  Ming-Dou Ker

Inventor： Shih-Hung Chen ,  Ming-Dou Ker

IPC: H02H9/00

CPC classification number: H01L27/0251 ,  H01L27/0292

Abstract: A circuit capable of providing electrostatic discharge (ESD) protection, the circuit comprising a first set of power rails comprising a first high power rail and a first low power rail, a first interface circuit between the first set of power rails, the first interface circuit having at least one gate electrode, a first ESD device comprising a terminal coupled to the at least one gate electrode of the first interface circuit, and a second ESD device comprising a terminal coupled to the at least one gate electrode of the first interface circuit, the first ESD device and the second ESD device being configured to maintain a voltage level at the at least one gate electrode of the first interface circuit at approximately a ground level when ESD occurs.

Abstract translation: 一种能够提供静电放电（ESD）保护的电路，所述电路包括包括第一高功率轨道和第一低功率轨道的第一组电力轨道，所述第一组电力轨道之间的第一接口电路，所述第一接口电路 具有至少一个栅电极，第一ESD器件，其包括耦合到所述第一接口电路的所述至少一个栅电极的端子，以及包括耦合到所述第一接口电路的所述至少一个栅电极的端子的第二ESD器件， 第一ESD器件和第二ESD器件被配置为当ESD发生时将第一接口电路的至少一个栅电极的电压电平保持在大致的接地电平。

公开(公告)号：US20070147105A1

公开(公告)日：2007-06-28

申请号：US11612093

申请日：2006-12-18

Applicant: Hsiang-Lan Lung ,  Rich Liu ,  Shih-Hung Chen ,  Yi-Chou Chen

Inventor： Hsiang-Lan Lung ,  Rich Liu ,  Shih-Hung Chen ,  Yi-Chou Chen

IPC: G11C11/00

CPC classification number: G11C8/10 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/53 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/165 ,  H01L45/1675

Abstract: A phase change memory cell includes first and second electrodes electrically coupled by a phase change element. At least a section of the phase change element comprises a higher reset transition temperature portion and a lower reset transition temperature portion. The lower reset transition temperature portion comprises a phase change region which can be transitioned, by the passage of electrical current therethrough, from generally crystalline to generally amorphous states at a lower temperature than the higher reset transition temperature portion. The phase change element may comprise an outer, generally tubular, higher reset transition temperature portion surrounding an inner, lower reset transition temperature portion.

Abstract translation: 相变存储单元包括由相变元件电耦合的第一和第二电极。 相变元件的至少一部分包括较高的复位转变温度部分和较低的复位转变温度部分。 下复位转变温度部分包括可以通过电流通过从相对于较高复位转变温度部分的较低温度的大致结晶到大致非晶状态的相变区域。 相变元件可以包括围绕内部，下部复位转变温度部分的外部，大体上管状的较高复位转变温度部分。

公开(公告)号：US20070109843A1

公开(公告)日：2007-05-17

申请号：US11621390

申请日：2007-01-09

Applicant: Hsiang Lan Lung ,  Shih-Hung Chen

Inventor： Hsiang Lan Lung ,  Shih-Hung Chen

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  H01L45/1691

Abstract: A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change element positioned between and electrically coupling the opposed contact elements of the electrodes to one another. The phase change element has a width, a length and a thickness. The length, the thickness and the width are less than a minimum photolithographic feature size of the process used to form the phase change memory cell. The size of the photoresist masks used in forming the memory cell may be reduced so that the length and the width of the phase change element are each less than the minimum photolithographic feature size.

Abstract translation: 相变存储器件包括具有第一和第二电极的光刻形成的相变存储器单元和位于彼此之间并将电极的相对接触元件彼此电耦合的相变元件。 相变元件具有宽度，长度和厚度。 长度，厚度和宽度小于用于形成相变存储器单元的工艺的最小光刻特征尺寸。 可以减小用于形成存储单元的光致抗蚀剂掩模的尺寸，使得相变元件的长度和宽度均小于最小光刻特征尺寸。

公开(公告)号：US20060284158A1

公开(公告)日：2006-12-21

申请号：US11424749

申请日：2006-06-16

Applicant: Hsiang-Lan Lung ,  Shih-Hung Chen

Inventor： Hsiang-Lan Lung ,  Shih-Hung Chen

IPC: H01L29/02

CPC classification number: H01L27/2436 ,  G11C13/0004 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1293 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683 ,  H01L45/1691

Abstract: An integrated circuit with an embedded memory comprises a substrate and a plurality of conductor layers arranged for interconnecting components of the integrated circuit. An intermediate layer in the plurality of conductor layers includes a first electrode having a top surface, a second electrode having a top surface, an insulating member between the first electrode and the second electrode. A bridge overlies the intermediate layer between the first and second electrodes across the insulating member, wherein the bridge comprises a programmable resistive memory material, such as a phase change material. A conductor in at least one layer in the plurality of conductor layers over said intermediate layer is connected to said bridge.

Abstract translation: 具有嵌入式存储器的集成电路包括衬底和布置用于互连集成电路的部件的多个导体层。 多个导体层中的中间层包括具有顶表面的第一电极，具有顶表面的第二电极，在第一电极和第二电极之间的绝缘构件。 桥跨过绝缘构件覆盖在第一和第二电极之间的中间层，其中桥包括可编程电阻存储器材料，例如相变材料。 在所述中间层上的多个导体层中的至少一层中的导体连接到所述桥。