公开(公告)号：US09368379B2

公开(公告)日：2016-06-14

申请号：US13419952

申请日：2012-03-14

Applicant: Shih-Hung Chen ,  Ying Xiao ,  Chin-Hsiang Lin

Inventor： Shih-Hung Chen ,  Ying Xiao ,  Chin-Hsiang Lin

IPC: G06F15/00 ,  G01B11/26 ,  H01L21/67 ,  H01L21/68 ,  H01L21/687

CPC classification number: H01L21/67259 ,  H01L21/681 ,  H01L21/68764

Abstract: A system and method of controlling a semiconductor wafer fabrication process. The method includes positioning a semiconductor wafer on a wafer support assembly in a wafer processing module. A signal is transmitted from a signal emitter positioned at a predetermined transmission angle relative to an axis normal to the wafer support assembly to check leveling of the wafer in the module, so that the signal is reflected from the wafer. The embodiment includes monitoring for the reflected signal at a predetermined reflectance angle relative to the axis normal to the wafer support assembly at a signal receiver. A warning indication is generated if the reflected signal is not received at the signal receiver.

Abstract translation: 一种控制半导体晶片制造工艺的系统和方法。 该方法包括将半导体晶片定位在晶片处理模块中的晶片支撑组件上。 信号从相对于垂直于晶片支撑组件的轴线以预定的传输角定位的信号发射器传输，以检查模块中晶片的调平，使得信号从晶片反射。 该实施例包括在信号接收器处相对于垂直于晶片支撑组件的轴以预定的反射角监视反射信号。 如果在信号接收器处未接收到反射信号，则会产生警告指示。

公开(公告)号：US09111597B2

公开(公告)日：2015-08-18

申请号：US13721523

申请日：2012-12-20

Applicant: Shih-Hung Chen

Inventor： Shih-Hung Chen

IPC: H01L23/48 ,  G11C8/10 ,  G11C5/02

CPC classification number: G11C8/10 ,  G11C5/025

Abstract: A memory device structure and method of fabricating the memory device structure is described. The memory device structure has a memory array disposed in a array level and peripheral circuitry, including decoders and other peripheral circuitry, disposed in a device level. The array of memory cells has a perimeter that defines a cylinder that extends above and beneath the array of memory cells. The decoders and the other peripheral circuitry or at least part of the decoders and the other peripheral circuitry are disposed within the cylinder in the device level. The memory device structure also includes a plurality of pads in a pad level. A first plurality of inter-level conductive lines electrically couples the decoders to the bit lines and word lines in the array of memory cells.

Abstract translation: 描述了一种用于制造存储器件结构的存储器件结构和方法。 存储器件结构具有设置在阵列级的存储器阵列和设置在器件级的外围电路，包括解码器和其它外围电路。 存储器单元阵列具有限定在存储器单元阵列上方和下方延伸的圆柱体的周边。 解码器和其它外围电路或解码器和其它外围电路的至少一部分设置在装置级内的气缸内。 存储器件结构还包括垫级别中的多个焊盘。 第一多个级间导电线将解码器电耦合到存储器单元阵列中的位线和字线。

公开(公告)号：US09082656B2

公开(公告)日：2015-07-14

申请号：US13294852

申请日：2011-11-11

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC: H01L27/115

CPC classification number: H01L27/1157 ,  H01L27/11578

Abstract: A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures.

Abstract translation: 一种用于存储器阵列的制造方法包括首先在多个半导体条上形成多层电介质材料，然后在开关晶体管区域中暴露多层叠层。 在开关晶体管区域中暴露的多层堆叠被处理以形成不同于介电电荷俘获结构的栅介质结构。 然后形成字线和选择线。 介质电荷俘获存储器单元的3D阵列包括存储器单元的NAND串的堆叠。 多个开关晶体管耦合到NAND串，开关晶体管包括栅极电介质结构，其中栅极电介质结构不同于介电电荷俘获结构。

公开(公告)号：US08987787B2

公开(公告)日：2015-03-24

申请号：US13443496

申请日：2012-04-10

Applicant: Shih-Hung Chen ,  Kuang-Yeu Hsieh ,  Cheng-Yuan Wang

Inventor： Shih-Hung Chen ,  Kuang-Yeu Hsieh ,  Cheng-Yuan Wang

IPC: H01L27/118 ,  H01L23/52 ,  H01L23/34 ,  H01L23/48 ,  H01L29/40 ,  H01L21/00 ,  H01L21/336 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L27/105 ,  H01L27/02

CPC classification number: H01L23/522 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0203 ,  H01L27/1052 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06177 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/73207 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/1431 ,  H01L2924/1435 ,  H01L2924/1443

Abstract: A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.

Abstract translation: 半导体结构包括彼此组装的第一和第二芯片。 第一芯片包括N个第一导线，M个第二导线设置在第一导线上，N个第三导线垂直于第二导线并平行于第一导线，N个第一导通孔连接到第一导电 线，连接到第二导线的M组第二通孔，以及连接到第三导线的N组第三通孔。 第二和第一导电线形成重叠区域。 第三导线和N组第三通孔包括分别设置在重叠区域的第一和第三区域中的至少两个组。 M组第二通孔包括分别设置在重叠区域的第二区域和第四区域中的至少两个组。

公开(公告)号：US08951862B2

公开(公告)日：2015-02-10

申请号：US13347331

申请日：2012-01-10

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC: H01L21/336

CPC classification number: H01L27/11582 ,  H01L29/7926

Abstract: The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.

Abstract translation: 该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。 诸如硅的导电线形成在堆叠的非易失性存储器结构之上。 字线沟槽分离出相邻的硅线。 由字线沟槽分隔的硅线被氧化，在字线沟槽中形成绝缘表面。 字线是在字线沟中制作的。

公开(公告)号：US08643078B2

公开(公告)日：2014-02-04

申请号：US13443417

申请日：2012-04-10

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

IPC: H01L29/788

CPC classification number: H01L23/3192 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a base, a stacked structure and a doped layer. The stacked structure is formed on the base, wherein the stacked structure comprises a plurality of conductive strips and a plurality of insulating strips, one of the conductive strips is located between adjacent two insulating strips, the stacked structure has a first side wall, and a long edge of the first side wall is extended along a channel direction. The doped layer is formed in the first side wall, wherein the doped layer is formed by an ion implantation applied to the first side wall, and an acute angle is contained between an implantation direction of the ion implantation and the first side wall.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括基极，层叠结构和掺杂层。 堆叠结构形成在基底上，其中堆叠结构包括多个导电条和多个绝缘条，其中一个导电条位于相邻的两个绝缘条之间，该堆叠结构具有第一侧壁和 第一侧壁的长边缘沿着通道方向延伸。 掺杂层形成在第一侧壁中，其中通过施加到第一侧壁上的离子注入形成掺杂层，并且在离子注入的注入方向和第一侧壁之间包含锐角。

公开(公告)号：US20130334575A1

公开(公告)日：2013-12-19

申请号：US13527259

申请日：2012-06-19

Applicant: Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

IPC: H01L27/10 ,  H01L21/768

CPC classification number: H01L27/11578 ,  H01L27/11565

Abstract: The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures.

Abstract translation: 该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。 在多个堆叠的非易失性存储器结构上制造部分氧化的材料线如硅。 通过从部分氧化的线的中间部分去除未氧化的线，在多个部分氧化的线的外部部分留下多条氧化线，在部分氧化的线中形成字线沟槽。 在多个堆叠的非易失性存储器结构中的字线沟槽中形成字线。

公开(公告)号：US20130277852A1

公开(公告)日：2013-10-24

申请号：US13451411

申请日：2012-04-19

Applicant: Shih-Hung Chen

Inventor： Shih-Hung Chen

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/16146 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2224/82

Abstract: A 3D stacked multichip module comprises a stack of W IC die. Each die has a patterned conductor layer, including an electrical contact region with electrical conductors and, in some examples, device circuitry over a substrate. The electrical conductors of the stacked die are aligned. Electrical connectors extend into the stack to contact landing pads on the electrical conductors to create a 3D stacked multichip module. The electrical connectors may pass through vertical vias in the electrical contact regions. The landing pads may be arranged in a stair stepped arrangement. The stacked multichip module may be made using a set of N etch masks with 2N-1 being less than W and 2N being greater than or equal to W, with the etch masks alternatingly covering and exposing 2n-1 landing pads for each mask n=1, 2 . . . N.

Abstract translation: 3D堆叠多芯片模块包括一堆W IC芯片。 每个管芯具有图案化导体层，其包括与电导体的电接触区域，并且在一些示例中包括衬底上的器件电路。 堆叠管芯的电导体对齐。 电连接器延伸到堆叠中以接触电导体上的着陆焊盘，以产生3D堆叠多芯片模块。 电连接器可以穿过电接触区域中的垂直通孔。 着陆垫可以布置成阶梯式的台阶。 堆叠的多芯片模块可以使用一组N个蚀刻掩模制成，其中2N-1小于W且2N大于或等于W，其中蚀刻掩模交替地覆盖并暴露每个掩模的2n-1个着陆焊盘n = 1，2。 。 。 N.

公开(公告)号：US20130214340A1

公开(公告)日：2013-08-22

申请号：US13401634

申请日：2012-02-21

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC: H01L29/68 ,  H01L21/283

CPC classification number: H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, and a first conductive layer. The first stacked structure is formed on the substrate and includes a conductive structure and an insulating structure, and the conductive structure is disposed adjacent to the insulating structure. The first conductive layer is formed on the substrate and surrounds two side walls and a part of the top portion of the first stacked structure for exposing a portion of the first stacked structure.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括基板，第一堆叠结构和第一导电层。 第一堆叠结构形成在基板上，并且包括导电结构和绝缘结构，并且导电结构邻近于绝缘结构设置。 第一导电层形成在基板上并且包围第一层叠结构的两个侧壁和顶部的一部分，用于暴露第一堆叠结构的一部分。

公开(公告)号：US08503213B2

公开(公告)日：2013-08-06

申请号：US13078311

申请日：2011-04-01

Applicant: Shih-Hung Chen ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Hang-Ting Lue

IPC: G11C5/06

CPC classification number: H01L27/11578 ,  G11C13/0002 ,  G11C16/0483 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/11573

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit lines at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of word lines, which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor strips on the stacks and the word lines.

Abstract translation: 3D存储器件包括多个由绝缘材料隔开的导电材料条带形式的脊形叠层，排列成可通过解码电路耦合到读出放大器的位线。 二极管与字符串的公共源选择端的字符串选择连接到位线。 导电材料条具有在脊形叠层的侧面上的侧表面。 可以耦合到行解码器的多个字线在多个脊形叠层上正交延伸。 存储元件位于堆叠上的半导体条的侧表面和字线之间的交叉点处的界面区域的多层阵列中。