公开(公告)号：US5987583A

公开(公告)日：1999-11-16

申请号：US959942

申请日：1997-10-29

Applicant: Joseph W. Triece ,  Sumit K. Mitra

Inventor： Joseph W. Triece ,  Sumit K. Mitra

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/35 ,  G06F9/355

CPC classification number: G06F9/30181 ,  G06F9/30101 ,  G06F9/35

Abstract: A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.

Abstract translation: 一种允许多个寻址模式同时最大化可用操作码和可寻址寄存器数量的系统。 该系统具有处理器架构方案，其允许通过使用虚拟寄存器地址对多个寻址模式进行编码。 该系统具有指令集，该指令集具有多个指令。 每个指令具有多个位，其中多个指令中的每一个中的多个位中的每一个都不是用于实现不同寻址模式的专用位。 多个指令中的每一个能够通过在处理器架构方案中寻址虚拟寄存器地址来实现不同的寻址模式。 由于不需要位来实现不同的寻址模式，所以操作码字段和寄存器地址字段的长度由操作码的数量和用户希望实现的可寻址寄存器的数量来确定。

公开(公告)号：US5764099A

公开(公告)日：1998-06-09

申请号：US611451

申请日：1996-03-05

Applicant: Kent Hewitt

Inventor： Kent Hewitt

IPC: G06F1/26 ,  H02J9/00 ,  H04L29/00 ,  G05F1/00

CPC classification number: H02J9/005

Abstract: According to the present invention, there is provided an integrated circuit useful in an electronic encoding device having a voltage source, a user interface and a transmitter. In one embodiment the integrated circuit includes a wake-up circuit which generates a signal responsive to an input received from the user interface; power switching logic which provides power from the voltage source to a non-regulated power bus and a voltage regulating circuit, the power switching logic being responsive to the signal from the wake-up circuit; a regulated power bus in communication with the voltage regulating circuit; non-volatile memory in communication with the regulated power bus; encoder logic in communication with the regulated power bus, the encoder logic having output logic which provides a signal to the transmitter.

Abstract translation: 根据本发明，提供了一种在具有电压源，用户接口和发送器的电子编码装置中有用的集成电路。 在一个实施例中，集成电路包括唤醒电路，其产生响应于从用户接口接收的输入的信号; 功率开关逻辑，其从电压源提供电力到非调节电源总线和电压调节电路，功率开关逻辑响应于来自唤醒电路的信号; 与电压调节电路通信的稳压电源总线; 与稳压电源总线通讯的非易失性存储器; 编码器逻辑与调节电源总线通信，编码器逻辑具有向发射机提供信号的输出逻辑。

公开(公告)号：US5455937A

公开(公告)日：1995-10-03

申请号：US268673

申请日：1994-06-30

Applicant: Eric Berman ,  Greg Italiano ,  Ajay Padgaonkar ,  Ray Allen

Inventor： Eric Berman ,  Greg Italiano ,  Ajay Padgaonkar ,  Ray Allen

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/26 ,  G06F11/267 ,  G06F15/78 ,  G11C7/00 ,  G01R31/28

CPC classification number: G06F9/30145 ,  G06F11/2236 ,  G06F11/261 ,  G06F15/7814 ,  G06F9/30167

Abstract: A microcontroller fabricated on a semiconductor chip has an on-chip EPROM program memory with programmable EPROM configuration fuses located in a limited number of addresses of the on-chip program memory, the condition of each of EPROM fuse being defined as blown or not blown according to the value of the bit stored in the respective address of the on-chip program memory. The operating modes of the microcontroller are configurable by appropriately programming at least some of the EPROM fuses. Testing of the microcontroller in at least some of the operating modes is achieved by using latches outside the program memory to emulate the EPROM fuses, while suppressing the capability to set the condition of the EPROM fuses during the testing. Upon completion of the testing, control of the operating modes of the microcontroller is returned to the EPROM fuses, and the latches are precluded from further emulating the EPROM fuses.

Abstract translation: 在半导体芯片上制造的微控制器具有片上EPROM程序存储器，其具有位于片上程序存储器的有限地址中的可编程EPROM配置熔丝，每个EPROM保险丝的条件被定义为被吹制或不被吹制 到存储在片上程序存储器的相应地址中的位的值。 微控制器的工作模式可以通过适当地编程至少一些EPROM保险丝进行配置。 在至少一些操作模式下对微控制器的测试通过使用程序存储器外部的锁存器来模拟EPROM保险丝，同时抑制在测试期间设置EPROM保险丝的状态的能力来实现。 完成测试后，控制微控制器的工作模式返回到EPROM保险丝，锁存器不再进一步仿真EPROM保险丝。

公开(公告)号：US5020030A

公开(公告)日：1991-05-28

申请号：US265409

申请日：1988-10-31

Applicant: Robert J. Huber

Inventor： Robert J. Huber

IPC: G11C14/00 ,  H01L27/108 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L27/115 ,  G11C14/00 ,  H01L27/108 ,  H01L29/792

Abstract: A silicon substrate with a drain area formed therein is used for the base of the device. A first polysilicon gate is disposed above the substrate with a layer of gate oxide therebetween. Adjacent to the first gate and contiguous to the same plane is a second polysilicon gate. The second gate and the substrate are separated by a layer of tunnel oxide and silicon nitride. The silicon nitride being used to store a charge. The state of the device is determined by the presence of a capacitance in the substrate generated by the charge on the silicon nitride. This device may function as a nonvolatile memory or a dynamic random access memory with the capability of capturing its DRAM state.

Abstract translation: 其中形成有漏极区的硅衬底用于器件的基底。 第一多晶硅栅极设置在衬底上方，其间具有一层栅极氧化物。 与第一个栅极相邻并且与相同的平面邻接的是第二个多晶硅栅极。 第二栅极和衬底被隧道氧化物层和氮化硅层隔开。 用于存储电荷的氮化硅。 器件的状态由在氮化硅上的电荷产生的衬底中的电容的存在来确定。 该装置可以用作具有捕获其DRAM状态的能力的非易失性存储器或动态随机存取存储器。

公开(公告)号：US20250060901A1

公开(公告)日：2025-02-20

申请号：US18938806

申请日：2024-11-06

Applicant: Microchip Technology Inc.

Inventor： Christopher I. W. NORRIE

IPC: G06F3/06

Abstract: A method for gather/scatter operations in a vector processor includes: (a) checking for a read port start signal and when received setting an increment count to zero; (b) initiating a memory read using a port's address register, and setting the increment count to increment count+1; (c) incrementing the port's address register by a port's stride register; (d) checking to see if the increment count is greater than or equal to a port's length register and when not so proceeding to (b); and (e) checking to see if the increment count is greater than or equal to a port's length register and when so proceeding to (a).

公开(公告)号：US12223322B2

公开(公告)日：2025-02-11

申请号：US17852304

申请日：2022-06-28

Applicant: Microchip Technology Inc.

Inventor： Aaron Severance ,  Jonathan W. Greene ,  Joel Vandergriendt

IPC: G06F9/30

Abstract: A method and apparatus for embedding a microprocessor in a programmable logic device (PLD), where the microprocessor has a logic unit that can operate in two modes. A first mode is a general purpose mode running at least one general purpose process related to the PLD, and a second mode is a fixed function mode emulating a fixed function for use by logic configured into a fabric of the PLD (fabric). A memory unit is coupled to the logic unit and to the fabric, and the fabric is operable for transferring signals with the logic unit in relation to the fixed function.

公开(公告)号：US12014068B2

公开(公告)日：2024-06-18

申请号：US17671423

申请日：2022-02-14

Applicant: Microchip Technology Inc.

Inventor： Peter John Waldemar Graumann

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0619 ,  G06F3/0673

Abstract: A system and method for double data rate (DDR) chip-kill decoding using an array of ECC erasure decoders operating in parallel to identify a location of a chip-kill event associated with a DDR memory device. The ECC erasure decoder that correctly identifies the chip-kill location is then used to decode subsequent DDR bursts transmitted from the DDR memory device.

公开(公告)号：US11892955B2

公开(公告)日：2024-02-06

申请号：US17741282

申请日：2022-05-10

Applicant: Microchip Technology Inc.

Inventor： Sanjay Goyal ,  Larrie Simon Carr ,  Patrick Bailey

IPC: G06F13/16 ,  G06F11/10 ,  G06F13/42

CPC classification number: G06F13/1621 ,  G06F11/1004 ,  G06F13/1668 ,  G06F13/4221

Abstract: System and method for analyzing CXL flits at read bypass detection logic to identify bypass memory read requests and transmitting the identified bypass memory read requests over a read request bypass path directly to a transaction/application layer of the CXL memory controller, wherein the read request bypass path does not include an arbitration/multiplexing layer and a link layer of the CXL memory controller, thereby reducing the latency inherent in a CXL memory controller.

公开(公告)号：US11881775B2

公开(公告)日：2024-01-23

申请号：US17244882

申请日：2021-04-29

Applicant: Microchip Technology Inc.

Inventor： Jason Rabb

IPC: H02M3/158 ,  H04Q1/28

CPC classification number: H02M3/158 ,  H04Q1/28

Abstract: A system and method for generating a low supply voltage and a high supply voltage from an input voltage, wherein the dependency of the high supply voltage magnitude on the magnitude of the input voltage is removed and the resulting high supply voltage magnitude is a multiple of the low supply voltage magnitude. The low supply voltage and the high voltage may be implemented in a power converter of a communication system comprising a plurality of subscriber line interface circuits (SLICs).

公开(公告)号：US11782871B2

公开(公告)日：2023-10-10

申请号：US17701582

申请日：2022-03-22

Applicant: Microchip Technology Inc.

Inventor： Christopher I. W. Norrie

IPC: G06F15/80

CPC classification number: G06F15/8061

Abstract: In one implementation a vector processor unit having preload registers for at least some of vector length, vector constant, vector address, and vector stride. Each preload register has an input and an output. All the preload register inputs are coupled to receive a new vector parameters. Each of the preload registers' outputs are coupled to a first input of a respective multiplexor, and the second input of all the respective multiplexors are coupled to the new vector parameters.