公开(公告)号：US20080252279A1

公开(公告)日：2008-10-16

申请号：US12021689

申请日：2008-01-29

Applicant: Shu Wang

Inventor： Shu Wang

IPC: G05F1/46

CPC classification number: H02M3/157

Abstract: A method of controlling at least one transistor of a DC voltage converter to regulate an output voltage of the DC converter, the method including determining whether the output voltage of the DC converter is within a first or second voltage range, the second voltage range including a desired value of the output voltage; if the output voltage is in the first voltage range, generating a control signal using a first control method performed by a first controller, the first controller receiving the output voltage and determining the control signal based on the value of the output voltage in the first voltage range; and if the output voltage is in the second range, generating a control signal using a second control method performed by a second controller, the second controller receiving the output voltage and determining the control signal based on the value of the output voltage in the second voltage range.

Abstract translation: 一种控制DC电压转换器的至少一个晶体管以调节DC转换器的输出电压的方法，所述方法包括确定DC转换器的输出电压是否在第一或第二电压范围内，第二电压范围包括 输出电压的期望值; 如果输出电压处于第一电压范围，则使用由第一控制器执行的第一控制方法产生控制信号，第一控制器接收输出电压并且基于第一电压中的输出电压的值来确定控制信号 范围; 并且如果所述输出电压处于所述第二范围内，则使用由第二控制器执行的第二控制方法产生控制信号，所述第二控制器接收所述输出电压并基于所述第二电压中的所述输出电压的值来确定所述控制信号 范围。

公开(公告)号：US07436728B2

公开(公告)日：2008-10-14

申请号：US11594689

申请日：2006-11-08

Applicant: Michel Harrand ,  Joseph Bulone

Inventor： Michel Harrand ,  Joseph Bulone

IPC: G11C7/00

CPC classification number: G11C11/40618 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/12 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096

Abstract: A method to manage fast random access of a DRAM memory is described. The method includes steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request and comparing the address of the bank concerned by a current request with the addresses of the N−1 banks previously requested. N is an integral number of cycles necessary for executing a request. If the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N−1 previous requests, then the method further includes steps of suspending and memorizing the current request until the previous request involving the same bank is executed, otherwise the current request is executed.

Abstract translation: 描述了管理DRAM存储器的快速随机存取的方法。 该方法包括以下步骤：将存储器划分为以读和写模式独立访问的存储体; 通过当前请求识别有关银行的地址，并将当前请求的有关银行的地址与先前请求的N-1个银行的地址进行比较。 N是执行请求所需的周期的整数。 如果当前请求的有关银行的地址等于对应于N-1个先前请求之一的银行的地址，则该方法还包括暂停和存储当前请求的步骤，直到涉及相同的先前请求 执行bank，否则执行当前请求。

公开(公告)号：US07436702B2

公开(公告)日：2008-10-14

申请号：US11469351

申请日：2006-08-31

Applicant: David Naura ,  Christophe Moreaux ,  Ahmed Kari ,  Pierre Rizzo

Inventor： David Naura ,  Christophe Moreaux ,  Ahmed Kari ,  Pierre Rizzo

IPC: G11C11/34

CPC classification number: G11C16/22

Abstract: A method protects against a global data erasure an integrated circuit comprising an electrically programmable data memory and a control unit to execute commands for reading or writing in the memory. The method includes the steps of providing, in the integrated circuit, electrically programmable reference memory cells, at putting the integrated circuit into service, storing, in the reference memory cells, bits of determined value forming an authorized combination of bits and, during the operation of the integrated circuit following its putting into service, reading and evaluating the reference memory cells and blocking the integrated circuit if the reference memory cells contain a forbidden combination of bits different from the authorized combination.

Abstract translation: 一种防止全局数据擦除的集成电路的方法，该集成电路包括电可编程数据存储器和控制单元，以执行用于读取或写入存储器的命令。 该方法包括以下步骤：在集成电路中提供电可编程参考存储器单元，在将集成电路投入使用时，在参考存储器单元中存储形成授权的位组合的确定值的位，并且在操作期间 如果参考存储器单元包含与授权组合不同的位的禁止组合，则集成电路在其投入使用之后，读取和评估参考存储器单元并阻塞集成电路。

公开(公告)号：US07421595B2

公开(公告)日：2008-09-02

申请号：US11083111

申请日：2005-03-17

Applicant: Olivier Ferrand ,  Jean-Michel Gril-Maffre

Inventor： Olivier Ferrand ,  Jean-Michel Gril-Maffre

IPC: G06F1/00 ,  G06F1/26

CPC classification number: G06F9/30079 ,  G06F9/3867 ,  G06F9/3869

Abstract: A microprocessor includes a computation unit having logic units for executing operations associated with determined instructions of a microprocessor instruction set and a control unit for interpreting the instructions and for controlling the logic units accordingly. An internal timer of the microprocessor is activated by the control unit in response to the execution of a dedicated standby instruction of the microprocessor instruction set. Responsive thereto, a timeout signal is delivered to the control unit so as to place the microprocessor in a standby state during a determined timeout period.

Abstract translation: 微处理器包括具有用于执行与所确定的微处理器指令集的指令相关联的操作的逻辑单元的计算单元和用于解释指令并相应地控制逻辑单元的控制单元。 响应于微处理器指令集的专用备用指令的执行，控制单元激活微处理器的内部定时器。 响应于此，超时信号被传送到控制单元，以便在确定的超时期间将微处理器置于待机状态。

公开(公告)号：US20080186748A1

公开(公告)日：2008-08-07

申请号：US12023333

申请日：2008-01-31

Applicant: Francis Cuellar ,  Bertrand Rivet

Inventor： Francis Cuellar ,  Bertrand Rivet

IPC: H02M3/04

CPC classification number: H02M1/34 ,  H02M3/158 ,  H02M2001/346 ,  Y02B70/1491

Abstract: A switched-mode power converter, including, between a first end of a main inductive element and a switch, a two-value inductive element automatically switching between its two values.

Abstract translation: 一种开关式功率转换器，包括在主电感元件的第一端和开关之间，两值感应元件在其两个值之间自动切换。

公开(公告)号：US20080180204A1

公开(公告)日：2008-07-31

申请号：US12020687

申请日：2008-01-28

Applicant: Aline Noire ,  Benjamin Therond

Inventor： Aline Noire ,  Benjamin Therond

IPC: H01F37/00

CPC classification number: H01F17/0013 ,  H01F27/34 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductive element formed of planar windings in different conductive levels, the windings being formed in a number of levels smaller by one unit than the number of windings, two of the windings being interdigited in a same level.

Abstract translation: 由不同导电水平的平面绕组形成的感应元件，绕组以与绕组数相比减小一个单位的数量级形成，其中两个绕组被互相指向同一水平。

公开(公告)号：US07404249B2

公开(公告)日：2008-07-29

申请号：US10268648

申请日：2002-10-10

Applicant: Pascal Gardes ,  Gérard Auriel

Inventor： Pascal Gardes ,  Gérard Auriel

IPC: H01F7/06

CPC classification number: H01L28/10 ,  H01F17/0006 ,  H01F41/041 ,  H01L2224/11 ,  Y10T29/4902 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for manufacturing an inductance in a monolithic circuit including a substrate of planar upper surface, including the steps of forming in the substrate a cavity substantially following the contour of the inductance to be formed, the cross-section of the cavity being deep with respect to its width; and filling the cavity with a conductive material.

Abstract translation: 一种用于在包括平面上表面的基板的单片电路中制造电感的方法，包括以下步骤：在所述基板中形成基本上遵循待形成的电感轮廓的空腔，所述空腔的横截面相对于 到它的宽度 并用导电材料填充空腔。

公开(公告)号：US20080157747A1

公开(公告)日：2008-07-03

申请号：US11998161

申请日：2007-11-28

Applicant: Raynald Achart ,  Laurent Gonthier

Inventor： Raynald Achart ,  Laurent Gonthier

IPC: G05F1/445

CPC classification number: H02M5/293 ,  Y10S323/902 ,  Y10S323/905

Abstract: A circuit for controlling the power in a load supplied by an A.C. voltage and directly connected to a first terminal of application of the A.C. voltage, including two isolated-gate bipolar transistors, connected in anti-parallel between a second terminal of application of the A.C. voltage and the load; circuitry for detecting the zero crossing of the A.C. supply voltage in a first direction; circuitry for generating, at each period of the supply voltage, a pulse of predetermined duration for controlling a first one of said transistors, the time of occurrence of the pulse being conditioned by the detection of the zero crossing of the A.C. voltage and by a desired power reference setting a variable delay of occurrence of the pulse with respect to the detected zero crossing; and circuitry for inverting and transferring said pulse to the second transistor.

Abstract translation: 一种用于控制由AC电压提供并直接连接到施加AC电压的第一端子的负载中的功率的电路，包括两个隔离栅双极晶体管，反相并联连接在AC的第二端 电压和负载; 用于检测交流电源电压在第一方向上的过零点的电路; 电路，用于在电源电压的每个周期产生用于控制所述晶体管中的第一个的预定持续时间的脉冲，通过检测交流电压的零交叉来调节脉冲的发生时间和期望的 功率参考设置相对于检测到的过零点的脉冲发生的可变延迟; 以及用于将所述脉冲反转并传送到第二晶体管的电路。

公开(公告)号：US07391449B2

公开(公告)日：2008-06-24

申请号：US10870336

申请日：2004-06-17

Applicant: Laurent Simony

Inventor： Laurent Simony

IPC: H04N9/64

CPC classification number: H04N5/335 ,  H04N5/361

Abstract: For each current image output from a pixel matrix, the digital words relative to at least one masked line of the matrix are processed to generate a current correction digital code. From this code, a black level compensation signal is generated and applied as an offset control on pixel signal amplification. If the current correct digital code does not differ from the code calculated for a previous image output by a predetermined amount, then the code for the previous image is instead used to generate the black level compensation signal.

Abstract translation: 对于从像素矩阵输出的每个当前图像，处理相对于矩阵的至少一个屏蔽线的数字字以产生电流校正数字码。 根据该代码，产生黑电平补偿信号，作为像素信号放大的偏移控制。 如果当前正确的数字代码与对于先前图像输出计算的代码没有不同的预定量，则用于先前图像的代码用于生成黑电平补偿信号。

公开(公告)号：US07388802B2

公开(公告)日：2008-06-17

申请号：US11423852

申请日：2006-06-13

Applicant: Sylvie Wuidart ,  Mathieu Lisart ,  Nicolas Demange

Inventor： Sylvie Wuidart ,  Mathieu Lisart ,  Nicolas Demange

IPC: G11C8/00 ,  G11C5/06 ,  G11C7/00 ,  G11C8/02 ,  G06F12/00

CPC classification number: G11C8/20 ,  G11C7/24 ,  G11C16/22

Abstract: A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.

Abstract translation: 存储器包括布置在存储器阵列中的存储单元，以及地址解码器，用于根据应用于存储器的读取地址将存储单元选择信号应用于存储器阵列。 存储器包括地址重构电路，其从存储器单元选择信号重建读取地址的至少一部分，并且提供能够检测影响选择信号的错误注入的第一重建地址。 特别但不排他地适用于芯片卡的集成电路。