公开(公告)号：US20070246763A1

公开(公告)日：2007-10-25

申请号：US11460346

申请日：2006-07-27

Applicant: Chao-Hsi Chung

Inventor： Chao-Hsi Chung

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/42376 ,  H01L27/10873 ,  H01L29/1037 ,  H01L29/4933 ,  H01L29/66651 ,  H01L29/66659

Abstract: A trench step channel cell transistor and a manufacture method thereof are disclosed. The transistor could be applied to increase the channel length thereof. The transistor comprises a step silicon layer formed by a selective growth, while the step silicon layer is located above the active area of the transistor.

Abstract translation: 公开了一种沟槽级沟道单元晶体管及其制造方法。 可以施加晶体管以增加其沟道长度。 晶体管包括通过选择性生长形成的阶梯硅层，而步进硅层位于晶体管的有源区之上。

公开(公告)号：US20070228460A1

公开(公告)日：2007-10-04

申请号：US11442259

申请日：2006-05-30

Applicant: Hsueh Che

Inventor： Hsueh Che

IPC: H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC classification number: H01L27/10888

Abstract: A contact plug structure for a checkerboard dynamic random access memory comprises a body portion, two leg portions connected to the body portion and a dielectric block positioned between the two leg portions. Each leg portion is electrically connected to a deep trench capacitor arranged in an S-shape manner with respect to the contact plug structure via a doped region isolated by a shallow trench isolation structure. Preferably, the body portion and the two leg portions can be made of the same conductive material selected from the group consisting of polysilicon, doped polysilicon, tungsten, copper and aluminum, while the dielectric block can be made of material selected from the group consisting of borophosphosilicate glass. Particularly, the contact plug can be prepared by dual-damascene technique. Since the overlapped area between the contact plug structure and a word line can be dramatically decreased, the bit line coupling (BLC) can be effectively reduced.

Abstract translation: 用于棋盘动态随机存取存储器的接触插头结构包括主体部分，连接到主体部分的两个腿部部分和位于两个腿部之间的介质块。 每个支脚部分经由由浅沟槽隔离结构隔离的掺杂区域相对于接触插塞结构电连接到以S形方式设置的深沟槽电容器。 优选地，主体部分和两个腿部分可以由选自多晶硅，掺杂多晶硅，钨，铜和铝的相同的导电材料制成，而介电块可以由选自以下的材料制成： 硼磷硅酸盐玻璃。 特别地，接触插塞可以通过双镶嵌技术制备。 由于可以显着地减小接触插塞结构和字线之间的重叠区域，所以可以有效地减少位线耦合（BLC）。

公开(公告)号：US07276753B2

公开(公告)日：2007-10-02

申请号：US11163600

申请日：2005-10-25

Applicant: Hsiao-Che Wu

Inventor： Hsiao-Che Wu

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10861 ,  H01L27/10867 ,  H01L27/10873 ,  H01L29/785

Abstract: A method of fabricating a dynamic random access memory cell is provided. A substrate having a patterned mask layer thereon and a deep trench therein is provided. The patterned mask layer exposes the deep trench. A deep trench capacitor is formed inside the deep trench. Thereafter, a trench is formed in the substrate on one side of the deep trench capacitor. The trench exposes a portion of the upper electrode of the deep trench capacitor and a portion of the substrate. After that, a semiconductor strip is formed in the trench. A gate dielectric layer is formed over the substrate to cover the exposed semiconductor strip and the substrate. A gate is formed over the gate dielectric layer such that the gate and the semiconductor strip crosses over each other, and the gate-covered portion of the semiconductor strip serves as a channel region.

Abstract translation: 提供一种制造动态随机存取存储单元的方法。 提供其上具有图案化掩模层并在其中具有深沟槽的衬底。 图案化掩模层暴露深沟槽。 在深沟槽内形成深沟槽电容器。 此后，在深沟槽电容器的一侧上的衬底中形成沟槽。 沟槽暴露了深沟槽电容器的上部电极的一部分和衬底的一部分。 之后，在沟槽中形成半导体条。 栅极电介质层形成在衬底上以覆盖暴露的半导体条和衬底。 栅极形成在栅极电介质层上，使得栅极和半导体条彼此交叉，并且半导体条的栅极覆盖部分用作沟道区。

公开(公告)号：US20070218638A1

公开(公告)日：2007-09-20

申请号：US11435848

申请日：2006-05-18

Applicant: Ting Wang

Inventor： Ting Wang

IPC: H01L21/336

CPC classification number: H01L29/42368 ,  H01L21/28141 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/7834

Abstract: A recessed gate structure comprises a semiconductor substrate, a recess positioned in the semiconductor substrate, a gate oxide layer positioned in the recess and a conductive layer positioned on the gate oxide layer, wherein the semiconductor substrate has a multi-step structure in the recess. The thickness of the gate oxide layer on one step surface can be different from that on another step surface of the multi-step structure. In addition, the recessed gate structure further comprises a plurality of doped regions positioned in the semiconductor substrate under the multi-step structure, and these doped regions may use different dosages and different types of dopants. There is a carrier channel in the semiconductor substrate under the recessed gate structure and the overall channel length of the carrier channel is substantially the summation of the lateral width and twice of the vertical depth of the recessed gate structure.

Abstract translation: 凹陷栅极结构包括半导体衬底，位于半导体衬底中的凹部，位于凹槽中的栅极氧化物层和位于栅极氧化物层上的导电层，其中半导体衬底在凹部中具有多级结构。 一步表面上的栅极氧化层的厚度可以与多步结构的另一台阶表面上的厚度不同。 此外，凹陷栅极结构还包括在多步结构下位于半导体衬底中的多个掺杂区域，并且这些掺杂区域可以使用不同的剂量和不同类型的掺杂剂。 在凹陷栅极结构下方的半导体衬底中存在载流子通道，并且载流子通道的整体沟道长度基本上是凹入栅极结构的横向宽度和垂直深度的两倍的总和。

公开(公告)号：US20070215915A1

公开(公告)日：2007-09-20

申请号：US11440075

申请日：2006-05-25

Applicant: Ting Wang

Inventor： Ting Wang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/1037 ,  H01L21/28114 ,  H01L21/28141 ,  H01L29/1045 ,  H01L29/42376 ,  H01L29/66659

Abstract: A multi-step gate structure comprises a semiconductor substrate having a multi-step structure, a gate oxide layer positioned on the multi-step structure and a conductive layer positioned on the gate oxide layer. Preferably, the gate oxide layer has different thicknesses on each step surface of the multi-step structure. In addition, the multi-step gate structure further comprises a plurality of doped regions positioned in the semiconductor substrate under the multi-step structure. The channel length of the multi-step gate structure is the summation of the lateral width and the vertical depth of the multi-step gate structure, which is dramatically increased such that problems originated from the short channel effect can be effectively solved. Further, the plurality of doped regions under the multi-step structure are prepared by implanting processes having different dosages and dopants, which can control the thickness of the gate oxide layer and the threshold voltage of the multi-step gate structure.

Abstract translation: 多级栅极结构包括具有多级结构的半导体衬底，位于多级结构上的栅极氧化物层和位于栅极氧化物层上的导电层。 优选地，栅极氧化物层在多步骤结构的每个台阶表面上具有不同的厚度。 此外，多步栅极结构还包括在多步结构下定位在半导体衬底中的多个掺杂区域。 多级栅极结构的沟道长度是多级栅极结构的横向宽度和垂直深度的总和，其显着增加，从而可以有效地解决源自短沟道效应的问题。 此外，通过注入具有不同剂量和掺杂剂的工艺来制备多步结构下的多个掺杂区域，其可以控制栅极氧化物层的厚度和多步栅极结构的阈值电压。

公开(公告)号：US20070141732A1

公开(公告)日：2007-06-21

申请号：US11401366

申请日：2006-04-11

Applicant: Kuan-Hsun Huang ,  Jen-Lang Lue

Inventor： Kuan-Hsun Huang ,  Jen-Lang Lue

IPC: H01L21/66

CPC classification number: H01L22/12

Abstract: A structural analysis method of deep trenches is provided. A substrate having a plurality of deep trenches is provided. A polishing process is performed on the substrate to form an incline in a partial region of the substrate to expose surface structures at different depths of the deep trenches. Then, a structural analysis of the surface structures at different depths of the deep trenches is performed to observe defects.

Abstract translation: 提供深沟的结构分析方法。 提供具有多个深沟槽的衬底。 在衬底上进行抛光处理以在衬底的部分区域中形成倾斜，以暴露深沟槽不同深度处的表面结构。 然后，对深沟槽不同深度的表面结构进行结构分析，观察缺陷。

公开(公告)号：US20070131982A1

公开(公告)日：2007-06-14

申请号：US11298836

申请日：2005-12-12

Applicant: Jai Sim ,  Jih Chou

Inventor： Jai Sim ,  Jih Chou

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/10894 ,  H01L27/10876 ,  H01L29/41783 ,  H01L29/66553 ,  H01L29/66621

Abstract: A memory cell structure comprises a semiconductor substrate, two stack structures positioned on the semiconductor substrate, two conductive spacers positioned on sidewalls of the two stack structures, a gate oxide layer covering a portion of the semiconductor substrate between the two conductive spacers and a gate structure positioned at least on the gate oxide layer. Particularly, each of two stack structures includes a first oxide block, a conductive block and a second oxide block, and the two conductive spacers are positioned at on the sidewall of the two conductive blocks of the two stack structures. The two conductive spacers are preferably made of polysilicon, and have a top end lower than the bottom surface of the second oxide block. In addition, a dielectric spacer is positioned on each of the two conductive spacers.

Abstract translation: 存储单元结构包括半导体衬底，位于半导体衬底上的两个堆叠结构，位于两个堆叠结构的侧壁上的两个导电间隔物，覆盖两个导电间隔物之间​​的半导体衬底的一部分的栅极氧化物层和栅极结构 至少位于栅极氧化物层上。 特别地，两个堆叠结构中的每一个包括第一氧化物块，导电块和第二氧化物块，并且两个导电间隔物位于两个堆叠结构的两个导电块的侧壁上。 两个导电间隔物优选由多晶硅制成，并且具有比第二氧化物块的底表面低的顶端。 此外，介电隔离物位于两个导电间隔物中的每一个上。

公开(公告)号：US07229880B2

公开(公告)日：2007-06-12

申请号：US10718008

申请日：2003-11-19

Applicant: Zhong Dong ,  Chuck Jang ,  Chunchieh Huang

Inventor： Zhong Dong ,  Chuck Jang ,  Chunchieh Huang

IPC: H01L21/336

CPC classification number: H01L29/511 ,  H01L21/28273

Abstract: An ONO-type inter-poly insulator is formed by depositing intrinsic silicon on an oxidation stop layer. In one embodiment, the oxidation stop layer is a nitridated top surface of a lower, and conductively-doped, polysilicon layer. In one embodiment, atomic layer deposition (ALD) is used to precisely control the thickness of the deposited, intrinsic silicon. Heat and an oxidizing atmosphere are used to convert the deposited, intrinsic silicon into thermally-grown, silicon dioxide. The oxidation stop layer impedes deeper oxidation. A silicon nitride layer and an additional silicon oxide layer are further deposited to complete the ONO structure before an upper, and conductively-doped, polysilicon layer is formed. In one embodiment, the lower and upper polysilicon layers are patterned to respectively define a floating gate (FG) and a control gate (CG) of an electrically re-programmable memory cell. In an alternative embodiment, after the middle, silicon nitride of the ONO structure is defined, another layer of intrinsic silicon is deposited, by way of for example, ALD. Heat and an oxidizing atmosphere are used to convert the second deposited, intrinsic silicon into thermally-grown, silicon dioxide. An ONO structure with two thermally-grown, and spaced apart, silicon oxide layers is thereby provided.

Abstract translation: 通过在氧化停止层上沉积本征硅来形成ONO型多晶硅绝缘体。 在一个实施方案中，氧化停止层是较低且导电掺杂的多晶硅层的氮化顶表面。 在一个实施例中，原子层沉积（ALD）用于精确控制沉积的本征硅的厚度。 使用热和氧化气氛将沉积的本征硅转化成热生长的二氧化硅。 氧化停止层阻碍更深的氧化。 在形成上部和导电掺杂的多晶硅层之前，进一步沉积氮化硅层和另外的氧化硅层以完成ONO结构。 在一个实施例中，下部和上部多晶硅层被图案化以分别限定电可重新编程的存储器单元的浮动栅极（FG）和控制栅极（CG）。 在替代实施例中，在中间形成ONO结构的氮化硅之后，通过例如ALD沉积另一层本征硅。 使用热和氧化气氛将第二沉积的本征硅转化成热生长的二氧化硅。 由此提供具有两个热生长和间隔开的氧化硅层的ONO结构。

公开(公告)号：US20070120171A1

公开(公告)日：2007-05-31

申请号：US11246447

申请日：2005-10-06

Applicant: Yue-Song He ,  Chung Leung ,  Jin-Ho Kim ,  Kwok Ng

Inventor： Yue-Song He ,  Chung Leung ,  Jin-Ho Kim ,  Kwok Ng

IPC: H01L29/788

CPC classification number: H01L29/42336 ,  G11C16/0458 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521

Abstract: A memory cell (110) has a plurality of floating gates (120L, 120R). The channel region (170) comprises a plurality of sub-regions (220L, 220R) adjacent to the respective floating gates, and a connection region (210) between the floating gates. The connection region has the same conductivity type as the source/drain regions (160) to increase the channel conductivity. Therefore, the floating gates can be brought closer together even though the inter-gate dielectric (144) becomes thick between the floating gates, weakening the control gate's (104) electrical field in the channel.

Abstract translation: 存储单元（110）具有多个浮动栅极（120L，120R）。 通道区域（170）包括与相应浮动栅极相邻的多个子区域（220L，220R），以及浮置栅极之间的连接区域（210）。 连接区域具有与源极/漏极区域（160）相同的导电类型以增加沟道导电性。 因此，即使栅极间电介质（144）在浮置栅极之间变厚，削弱了沟道中的控制栅极（104）电场，浮动栅极也可以更靠近在一起。

公开(公告)号：US20070092806A1

公开(公告)日：2007-04-26

申请号：US11254729

申请日：2005-10-21

Applicant: Chun Lin

Inventor： Chun Lin

IPC: G03C5/00 ,  G03F1/00

CPC classification number: G03F1/28 ,  G03F1/50 ,  G03F7/70283

Abstract: A mask at frequency domain comprises a plurality of amplitude patterns positioned on a first surface of the mask and a plurality of phase patterns positioned on a second surface of the mask. The amplitude patterns have different vertical thicknesses to change the amplitude of an exposing light, and the phase patterns have different vertical thicknesses to change the phase of the exposing light. Preferably, the amplitude patterns are made of inorganic material, such as molybdenum silicide (MoSi), and the phase patterns are made of transparent material, such as quartz. The amplitude patterns and phase patterns are the Fourier transform of a circuit layout, and their numbers and positions are correspondent with each other.

Abstract translation: 在频域处的掩模包括位于掩模的第一表面上的多个幅度图案和位于掩模的第二表面上的多个相位图案。 幅度图案具有不同的垂直厚度以改变曝光光的幅度，并且相位图案具有不同的垂直厚度以改变曝光光的相位。 优选地，幅度图案由诸如硅化钼（MoSi）的无机材料制成，并且相图由诸如石英的透明材料制成。 幅度图案和相位图案是电路布局的傅里叶变换，它们的数量和位置彼此对应。