公开(公告)号：US08592686B2

公开(公告)日：2013-11-26

申请号：US11547715

申请日：2005-04-04

Applicant: Atsushi Kobayashi ,  Kazuo Umeda ,  Wataru Gotou ,  Takahiro Sahara ,  Susumu Nakazawa ,  Kiyoshi Takeuchi ,  Takayuki Terauchi

Inventor： Atsushi Kobayashi ,  Kazuo Umeda ,  Wataru Gotou ,  Takahiro Sahara ,  Susumu Nakazawa ,  Kiyoshi Takeuchi ,  Takayuki Terauchi

IPC: H05K1/00

CPC classification number: H05K3/4691 ,  H05K3/0052 ,  H05K3/4069 ,  H05K3/4614 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2203/0169 ,  H05K2203/061

Abstract: A method for manufacturing a printed circuit board assembled panel by a simple process with an excellent material yield and a high conforming product rate. Unit printed circuit boards previously manufactured are arranged in a frame in a prescribed relationship. Then, the printed circuit boards are fixed to one another, and the printed circuit board and the frame body are fixed to one another.

Abstract translation: 一种通过简单的方法制造印刷电路板组装面板的方法，其具有优异的材料产率和高的一致性产品率。 先前制造的单元印刷电路板以规定的关系布置在框架中。 然后，印刷电路板彼此固定，并且印刷电路板和框架体彼此固定。

公开(公告)号：US20130031095A1

公开(公告)日：2013-01-31

申请号：US13556415

申请日：2012-07-24

Applicant: Kiyoshi Takeuchi

Inventor： Kiyoshi Takeuchi

IPC: G06F17/30

CPC classification number: G06F16/35

Abstract: A computer-readable recording medium has an entry support program embodied therein for causing a computer to perform detecting text being entered, extracting text examples corresponding to the detected text from a storage unit, the storage unit storing text examples and frequencies of use of the text examples such that the frequencies of use are associated with the respective text examples, classifying the extracted text examples into text-example groups each containing one or more text examples based on comparison of letters included in the extracted text examples, determining display order of the text-example groups, based on the frequencies of use that are associated in the storage unit with text examples belonging to the text-example groups, and displaying the extracted text examples in the determined display order.

Abstract translation: 一种计算机可读记录介质，其中具有入口支持程序，用于使计算机执行正在输入的检测文本，从存储单元提取与检测到的文本相对应的文本示例，存储单元存储文本的示例和使用频率 示例使得使用频率与各个文本示例相关联，根据提取的文本示例中包含的字母的比较将所提取的文本示例分类为每个包含一个或多个文本示例的文本示例组，确定文本的显示顺序 - 基于在存储单元中与使用属于文本示例组的文本示例相关联的使用频率的示例组，并且以确定的显示顺序显示所提取的文本示例。

公开(公告)号：USD660333S1

公开(公告)日：2012-05-22

申请号：US29414316

申请日：2012-02-27

Applicant: Kiyoshi Takeuchi ,  Takaaki Kobayashi

Designer： Kiyoshi Takeuchi ,  Takaaki Kobayashi

公开(公告)号：US08050895B2

公开(公告)日：2011-11-01

申请号：US11659972

申请日：2005-08-10

Applicant: Kiyoshi Takeuchi

Inventor： Kiyoshi Takeuchi

IPC: G06F17/10

CPC classification number: G06F17/504 ,  G06F17/5036

Abstract: A variation simulation system providing for facilitated circuit design with suppressed deterioration in performance otherwise caused by variations. A variation analysis unit 100 extracts statistical features of variations from a large number of samples beforehand. A model analysis unit 200 checks response of a circuit simulation output to parameter variations. A fitting execution unit 300 collates the information, obtained in this manner, to each other to determine the manner of variations of the parameters which will reproduce statistical features of the device samples.

Abstract translation: 一种变化模拟系统，其提供便利的电路设计，抑制性能劣化，否则由变化引起。 变化分析单元100预先从大量样本中提取变化的统计特征。 模型分析单元200检查电路仿真输出对参数变化的响应。 装配执行单元300将以这种方式获得的信息彼此对准，以确定将再现装置样本的统计特征的参数的变化方式。

公开(公告)号：US20100289091A1

公开(公告)日：2010-11-18

申请号：US12095663

申请日：2006-12-01

Applicant: Koichi Takeda ,  Kiyoshi Takeuchi

Inventor： Koichi Takeda ,  Kiyoshi Takeuchi

IPC: H01L27/088 ,  H01L21/8239

CPC classification number: H01L21/845 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  Y10S257/903

Abstract: A semiconductor device is provided with an SRAM cell unit. The SRAM cell unit is provided with a data storing section composed of a pair of drive transistors and a pair of load transistors; a data write section composed of a pair of access transistors; and a data read section composed of an access transistor and a drive transistor. Each of the transistors is provided with a semiconductor layer protruding from a base plane; a gate electrode extending on the both facing side planes over the semiconductor layer from above; a gate insulating film between a gate electrode and a semiconductor layer; and a source/drain region. Each semiconductor layer is arranged to have its longitudinal direction along a first direction. In the adjacent SRAM cell units in the first direction, all the corresponding transistors have the semiconductor layer of one transistor on a center line which is along the first direction of the semiconductor layer of the other transistor.

Abstract translation: 半导体器件设置有SRAM单元单元。 SRAM单元单元设置有由一对驱动晶体管和一对负载晶体管组成的数据存储部; 由一对存取晶体管组成的数据写入部分; 以及由存取晶体管和驱动晶体管构成的数据读取部。 每个晶体管设置有从基底面突出的半导体层; 从上方在半导体层上方的两面相对的侧面上延伸的栅电极; 在栅电极和半导体层之间的栅极绝缘膜; 和源极/漏极区域。 每个半导体层被布置成沿着第一方向具有其纵向方向。 在第一方向的相邻SRAM单元单元中，所有对应的晶体管都具有沿着另一个晶体管的半导体层的第一方向的中心线上的一个晶体管的半导体层。

公开(公告)号：US07815441B2

公开(公告)日：2010-10-19

申请号：US11547690

申请日：2005-04-04

Applicant: Atsushi Kobayashi ,  Kazuo Umeda ,  Wataru Gotou ,  Susumu Nakazawa ,  Kiyoshi Takeuchi ,  Takayuki Terauchi

Inventor： Atsushi Kobayashi ,  Kazuo Umeda ,  Wataru Gotou ,  Susumu Nakazawa ,  Kiyoshi Takeuchi ,  Takayuki Terauchi

IPC: H01R12/00

CPC classification number: H05K3/4691 ,  H05K3/0052 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/0187 ,  H05K2201/0919 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2203/0169 ,  H05K2203/061

Abstract: A rigid-flexible board and a method for manufacturing the same can be provided, whereby the material yield ratio can be enhanced and the productive yield can be also enhanced. A rigid board with a step for connection and a flexible board with a connector at the edge thereof are formed independently. Then, the connecting area is spot facing processed so that the depth of the thus obtained depressed portion is equal to or lower than the thickness of the flexible board. The connector of the flexible board is electrically connected to the vertical wiring area of the depressed portion.

Abstract translation: 可以提供刚性柔性板及其制造方法，从而可以提高材料屈服比，并且还可以提高生产率。 独立地形成具有用于连接的台阶的刚性板和在其边缘处具有连接器的柔性板。 然后，连接区域被加工成正面，使得如此获得的凹陷部分的深度等于或低于柔性板的厚度。 柔性板的连接器电连接到凹陷部分的垂直布线区域。

公开(公告)号：US20100012033A1

公开(公告)日：2010-01-21

申请号：US12096585

申请日：2006-11-30

Applicant: Masao Marunaka ,  Takayuki Tsuchiya ,  Atsuhiro Terakura ,  Kiyoshi Takeuchi

Inventor： Masao Marunaka ,  Takayuki Tsuchiya ,  Atsuhiro Terakura ,  Kiyoshi Takeuchi

IPC: C23C16/513

CPC classification number: H01J37/3266 ,  C23C14/35 ,  H01J37/32009

Abstract: A sheet plasma film forming apparatus includes: a pressure reducing container; a plasma gun; an anode; plasma flowing means; a sheet plasma converting chamber as part of the pressure reducing container; a pair of permanent magnets which forms a sheet-shaped plasma; and a film forming chamber as a part of the pressure reducing container. The pressure reducing container includes first and second bottle neck portions that are openings of the film forming chamber formed such that the plasma flows from the sheet plasma converting chamber through the first bottle neck portion to the film forming chamber, and the flown sheet-shaped plasma flows through the second bottle neck portion to the anode. In the thickness direction of the sheet-shaped plasma, a size of the first and second bottle neck portions is smaller than an internal size of the film forming chamber.

Abstract translation: 片状等离子体膜形成装置包括：减压容器; 等离子枪 阳极; 等离子体流动装置; 作为减压容器的一部分的片状等离子体转换室; 形成片状等离子体的一对永久磁铁; 以及作为减压容器的一部分的成膜室。 减压容器包括第一和第二瓶颈部分，其是成膜室的开口，其形成为使得等离子体从片状等离子体转换室通过第一瓶颈部分流到成膜室，并且流动的片状等离子体 流过第二瓶颈部分到阳极。 在片状等离子体的厚度方向上，第一和第二瓶颈部的尺寸小于成膜室的内部尺寸。

公开(公告)号：US20090014795A1

公开(公告)日：2009-01-15

申请号：US11658564

申请日：2005-07-14

Applicant: Risho Koh ,  Katsuhiko Tanaka ,  Shigeharu Yamagami ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda

Inventor： Risho Koh ,  Katsuhiko Tanaka ,  Shigeharu Yamagami ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A π gate FinFET structure having reduced variations in off-current and parasitic capacitance and a method for production thereof are provided. The structure of an element is improved so that an off-current suppressing capability can be exhibited more strongly. A field effect transistor, wherein a first insulating film and a semiconductor region are provided so as to protrude upward with respect to the flat surface of a base, the field effect transistor has a gate electrode, a gate insulating film and a source/drain region, and a channel is formed at least on the side surface of the semiconductor region, wherein that the first insulating film is provided on an etch stopper layer composed of a material having an etching rate lower than at least the lowermost layer of the first insulating film for etching under a predetermined condition.

Abstract translation: 提供了一种具有减小的截止电流和寄生电容的变化的p型门FinFET结构及其制造方法。 改善了元件的结构，使得能够更强烈地显示出截止电流的能力。 一种场效应晶体管，其中第一绝缘膜和半导体区域设置成相对于基底的平坦表面向上突出，所述场效应晶体管具有栅极电极，栅极绝缘膜和源极/漏极区域 并且至少在所述半导体区域的侧表面上形成沟道，其中所述第一绝缘膜设置在由蚀刻速率低于所述第一绝缘膜的最下层的蚀刻速率的材料构成的蚀刻停止层上 用于在预定条件下蚀刻。

公开(公告)号：US20070198235A1

公开(公告)日：2007-08-23

申请号：US11659972

申请日：2005-08-10

Applicant: Kiyoshi Takeuchi

Inventor： Kiyoshi Takeuchi

IPC: G06F17/10

CPC classification number: G06F17/504 ,  G06F17/5036

Abstract: A variation simulation system providing for facilitated circuit design with suppressed deterioration in performance otherwise caused by variations. A variation analysis unit 100 extracts statistical features of variations from a large number of samples beforehand. A model analysis unit 200 checks response of a circuit simulation output to parameter variations. A fitting execution unit 300 collates the information, obtained in this manner, to each other to determine the manner of variations of the parameters which will reproduce statistical features of the device samples.

Abstract translation: 一种变化模拟系统，其提供便利的电路设计，抑制性能劣化，否则由变化引起。 变化分析单元100预先从大量样本中提取变化的统计特征。 模型分析单元200检查电路仿真输出对参数变化的响应。 装配执行单元300将以这种方式获得的信息彼此对准，以确定将再现装置样本的统计特征的参数的变化方式。

公开(公告)号：US20070187682A1

公开(公告)日：2007-08-16

申请号：US10569451

申请日：2004-08-27

Applicant: Kiyoshi Takeuchi ,  Koji Watanabe ,  Koichi Terashima ,  Atsushi Ogura ,  Toru Tatsumi ,  Koichi Takeda ,  Masahiro Nomura ,  Masayasu Tanaka ,  Shigeharu Yamagami ,  Hitoshi Wakabayashi

Inventor： Kiyoshi Takeuchi ,  Koji Watanabe ,  Koichi Terashima ,  Atsushi Ogura ,  Toru Tatsumi ,  Koichi Takeda ,  Masahiro Nomura ,  Masayasu Tanaka ,  Shigeharu Yamagami ,  Hitoshi Wakabayashi

IPC: H01L29/04

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7854

Abstract: There is provided a semiconductor device comprising an n-type and a p-type field effect transistors, meeting the conditions that in terms of a crystal orientation of the protruding semiconductor region constituting the n-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {100} plane substantially orthogonal to the {100} plane, and that in terms of a crystal orientation of the protruding semiconductor region constituting the p-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {110} plane substantially orthogonal to the {100} plane.

Abstract translation: 提供一种包括n型和p型场效应晶体管的半导体器件，满足以下条件：就组成n型场效应晶体管的突出半导体区域的晶体取向而言，其平行于衬底的平面 基本上是{100}面，其侧面是与{100}面大致正交的{100}面，就构成p型场效应晶体管的突出半导体区域的晶体取向而言，其平面 与基板平行的基本上是{100}平面，其侧面是与{100}平面基本正交的{110}平面。