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    Semiconductor device and method of manufacturing the same
    2.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08124976B2

    公开(公告)日：2012-02-28

    申请号：US12095663

    申请日：2006-12-01

    申请人： Koichi Takeda ,  Kiyoshi Takeuchi

    发明人： Koichi Takeda ,  Kiyoshi Takeuchi

    IPC分类号： H01L27/11

    CPC分类号： H01L21/845 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  Y10S257/903

    摘要： The present invention provides a semiconductor device including SRAM cell units each including a data holding section made up of a pair of driving transistors and a pair of load transistors, a data write section made up of a pair of access transistors, and a data read section made up of an access transistor and a driving transistor, wherein each of the transistors includes a semiconductor layer projecting upward from a base plane, a gate electrode extending from a top to opposite side surfaces of the semiconductor layer so as to stride the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and source/drain areas, a longitudinal direction of each of the semiconductor layers is provided along a first direction, and for all the corresponding transistors between the SRAM cell units adjacent to each other in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer along the first direction in the other transistor.

    摘要翻译： 本发明提供了包括SRAM单元单元的半导体器件，每个SRAM单元包括由一对驱动晶体管和一对负载晶体管构成的数据保持部分，由一对存取晶体管构成的数据写入部分和数据读取部分 由存取晶体管和驱动晶体管构成，其中每个晶体管包括从基板向上突出的半导体层，从半导体层的顶部延伸到相对侧表面的栅电极，以跨越半导体层， 栅极电极和半导体层之间的栅极绝缘膜以及源极/漏极区域，沿着第一方向设置每个半导体层的纵向方向，并且对于彼此相邻的SRAM单元单元之间的所有对应的晶体管 在第一方向上，一个对应的晶体管中的半导体层位于半导体1a的中心线上 沿另一个晶体管的第一个方向。

    Semiconductor device with fin-type field effect transistor and manufacturing method thereof.
    3.
    发明授权
    Semiconductor device with fin-type field effect transistor and manufacturing method thereof. 失效
    具有鳍式场效应晶体管的半导体器件及其制造方法。

    公开(公告)号：US07719043B2

    公开(公告)日：2010-05-18

    申请号：US11632352

    申请日：2005-07-04

    申请人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

    发明人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/7851

    摘要： The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a part of the semiconductor substrate, and an insulating film on the shallow substrate flat surface; and the protrusive semiconductor layer of the Fin type FET is formed of a portion protruding from the insulating film of the semiconductor raised portion.

    摘要翻译： 本发明涉及一种半导体器件，其包括具有从衬底平面突出的突出半导体层的鳍型场效应晶体管（FET），形成为跨越突出半导体层的栅极电极，栅极电极 所述突出半导体层以及设置在所述突出半导体层中的源极和漏极区域，其中所述半导体器件在半导体衬底上具有具有鳍型FET的元件形成区域，设置在所述半导体衬底上的沟槽，用于将所述元件形成区域 来自另一个元件形成区域，以及沟槽中的元件隔离绝缘膜; 元件形成区域具有通过挖掘到比沟槽的底表面浅的深度而比半导体衬底的上表面更深的深浅的衬底平坦表面，从衬底平坦表面突出并形成的半导体凸起部分 的半导体衬底，以及在浅衬底平面上的绝缘膜; 并且鳍式FET的突出半导体层由从半导体凸起部分的绝缘膜突出的部分形成。

    Semiconductor device and method for manufacturing same
    4.
    发明授权
    Semiconductor device and method for manufacturing same 有权
    半导体装置及其制造方法

    公开(公告)号：US07701018B2

    公开(公告)日：2010-04-20

    申请号：US10593300

    申请日：2005-03-22

    申请人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

    发明人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

    IPC分类号： H01L27/088

    CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/6681 ,  H01L2029/7858

    摘要： A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.

    摘要翻译： 一种包括第一半导体区域和第二半导体区域的半导体器件，（a）其中场效应晶体管由包括从衬底向上突出的至少一个半导体层的第一半导体区域，栅电极， 通过绝缘膜形成，使得栅电极跨越设置在栅电极两侧的半导体层中的半导体层和源极/漏极区，由此沟道区是 形成在所述半导体层的至少两侧，（b），其中所述第二半导体区域包括从所述衬底向上突出的半导体层，并且至少相对于与沟道垂直的方向的两端处的所述第一半导体区域相对 电流方向和面对第一半导体区域的半导体层的侧表面平行于沟道电流方向。

    SYSTEM, METHOD AND PROGRAM FOR DETERMINING WORST CONDITION OF CIRCUIT OPERATION
    6.
    发明申请
    SYSTEM, METHOD AND PROGRAM FOR DETERMINING WORST CONDITION OF CIRCUIT OPERATION 审中-公开
    用于确定电路运行条件的系统，方法和程序

    公开(公告)号：US20100076741A1

    公开(公告)日：2010-03-25

    申请号：US12527862

    申请日：2008-02-13

    申请人： Kiyoshi Takeuchi

    发明人： Kiyoshi Takeuchi

    IPC分类号： G06F17/50 ,  G06F17/18

    CPC分类号： G06F17/504

    摘要： A system for determining a worst condition, wherein, in a model for which one or more parameters included in a model function that simulates a circuit performance index are random variable(s) to simulate the circuit performance index and fluctuations thereof, the parameter(s) for which the circuit performance index assumes a maximum or minimum value that is to be assumed from the viewpoint of designing is determined as the worst condition; the system comprises a worst condition search unit that searches for a point, having a maximum or minimum value of the circuit performance index, on an equi-probability surface corresponding to a preset good product ration within a space defined by the parameter(s); the point thus searched being determined as the worst condition.

    摘要翻译： 一种用于确定最差状况的系统，其中，在模拟包括在模拟电路性能指标的模型函数中的一个或多个参数的模型中，用于模拟电路性能指标及其波动的随机变量， ）将电路性能指标设定为从设计的观点假设的最大值或最小值被确定为最差条件; 所述系统包括最差条件搜索单元，其在具有所述电路性能指标的最大值或最小值的点上，在对应于由所述参数限定的空间内的预设好产品比例的等概率表面上进行搜索; 这样搜索的点被确定为最差条件。

    Azo dye compound
    7.
    发明授权
    Azo dye compound 有权
    偶氮染料化合物

    公开(公告)号：US07629459B2

    公开(公告)日：2009-12-08

    申请号：US11280399

    申请日：2005-11-17

    申请人： Katsumi Kobayashi ,  Yasuhiro Ishiwata ,  Nobuo Seto ,  Kiyoshi Takeuchi

    发明人： Katsumi Kobayashi ,  Yasuhiro Ishiwata ,  Nobuo Seto ,  Kiyoshi Takeuchi

    IPC分类号： C07D487/04 ,  C09B29/00

    CPC分类号： C07D487/04

    摘要： A compound represented by formula (I):Formula (I) wherein Z1 is atoms necessary for forming an aromatic ring; Z2 is atoms necessary for forming an aromatic hetero ring; V1 and V2 each are a substituent, and at least one of V1 and V2 is a hydroxyl, primary- or secondary- or tertiary-amino, acylamino, or sulfonamido group; r is 1 to 4; s is 1 to 4; the ring formed by Z1 or Z2 may have a substituent other than V1 or V2; M1 is a counter ion; m1 is the number necessary for neutralizing charge; and X1 and X2 each are a carbon or hetero atom, and at least one of X1 and X2 is a hetero atom.

    摘要翻译： 由式（I）表示的化合物：式（I）其中Z 1是形成芳环所必需的原子; Z2是形成芳族杂环所必需的原子; V1和V2各自为取代基，V1和V2中的至少一个为羟基，伯或仲或叔氨基，酰氨基或亚磺酰氨基; r为1〜4; s是1到4; 由Z1或Z2形成的环可以具有除V1或V2以外的取代基; M1是抗衡离子; m1是中和电荷所需的数字; X 1和X 2各自为碳原子或杂原子，X 1和X 2中的至少一个为杂原子。

    Fin-type field effect transistor, semiconductor device and manufacturing process therefor
    8.
    发明申请
    Fin-type field effect transistor, semiconductor device and manufacturing process therefor 有权
    鳍型场效应晶体管，半导体器件及其制造工艺

    公开(公告)号：US20090134454A1

    公开(公告)日：2009-05-28

    申请号：US11921685

    申请日：2006-06-05

    申请人： Kiyoshi Takeuchi ,  Katsuhiko Tanaka

    发明人： Kiyoshi Takeuchi ,  Katsuhiko Tanaka

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785

    摘要： A constant distance can be maintained between source/drain regions without providing a gate side wall by forming a gate electrode comprising an eaves structure, and a uniform dopant concentration is kept within a semiconductor by ion implantation. As a result, a FinFET excellent in element properties and operation properties can be obtained. A field effect transistor, wherein a gate structure body is a protrusion that protrudes toward source and drain regions sides in a channel length direction and has a channel length direction width larger than that of the part adjacent to the insulating film in a gate electrode, and the protrusion comprises an eaves structure formed by the protrusion that extends in a gate electrode extending direction on the top surface of the semiconductor layer.

    摘要翻译： 通过形成包括檐结构的栅电极，通过离子注入将均匀的掺杂剂浓度保持在半导体内，可以在源极/漏极区之间保持恒定的距离而不提供栅极侧壁。 结果，可以获得元件性能和操作性能优异的FinFET。 一种场效应晶体管，其中栅极结构体是在沟道长度方向上朝向源极和漏极区域侧突出的突起，并且沟道长度方向宽度大于栅电极中与绝缘膜相邻的部分的沟道长度方向宽度;以及 突起包括由在半导体层的顶表面上沿栅电极延伸方向延伸的突起形成的檐结构。

    Field effect transistor and method for producing the same
    9.
    发明申请
    Field effect transistor and method for producing the same 审中-公开
    场效应晶体管及其制造方法

    公开(公告)号：US20070158700A1

    公开(公告)日：2007-07-12

    申请号：US10587845

    申请日：2005-01-28

    申请人： Risho Koh ,  Katsuhiko Tanaka ,  Kiyoshi Takeuchi

    发明人： Risho Koh ,  Katsuhiko Tanaka ,  Kiyoshi Takeuchi

    IPC分类号： H01L29/76

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7854 ,  H01L29/78609

    摘要： A field effect transistor comprising: a semiconductor layer projecting from the plane of a base; a gate electrode provided on opposite side surfaces of the semiconductor layer; a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer; and source/drain regions where a first conductivity type impurity is introduced, wherein the semiconductor layer has a channel forming region in a portion sandwiched between the source/drain regions, and has in the upper part of the semiconductor layer in the channel forming region a channel impurity concentration adjusting region of which the concentration of a second conductivity type impurity is higher than that in the lower part of the semiconductor layer, and in the channel impurity concentration adjusting region, a channel is formed in a side surface portion facing the gate insulating film of the semiconductor layer in the channel impurity concentration adjusting region in a state of operation in which a signal voltage is applied to the gate electrode.

    摘要翻译： 一种场效应晶体管，包括：从基底的平面突出的半导体层; 设置在所述半导体层的相对侧表面上的栅电极; 介于栅电极和半导体层的侧表面之间的栅极绝缘膜; 以及引入第一导电型杂质的源极/漏极区域，其中半导体层在夹在源极/漏极区域之间的部分中具有沟道形成区域，并且在沟道形成区域a中的半导体层的上部 沟道杂质浓度调整区域，其中第二导电类型杂质的浓度高于半导体层的下部，并且在沟道杂质浓度调节区域中，在面向栅极绝缘体的侧表面部分中形成沟道 在对栅电极施加信号电压的工作状态下的沟道杂质浓度调整区域中的半导体层的膜。